LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN XiLu.T Cop -2. Digitized by the Internet Archive in 2013 http://archive.org/details/illiaciiicompute475nord 5/o. n Report No. hi 5 COO-2118-0Q22 ILLIAC III COMPUTER SYSTEM MANUAL: TAXICRINIC PROCESSOR VOLUME 2 by Bernard J. Nordmann, Jr, m UB^ I OEM SEP 3 19T1 August 2U, 1971 COO-2118-0022 Report No. ^75 ILLIAC III COMPUTER SYSTEM MANUAL: TAXICRINIC PROCESSOR VOLUME 2 by Bernard J. Nordmann, Jr. August 2k, 1971 Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported "by Contract AT(ll-l)-10l8 with the U.S, Atomic Energy Commission through September 30, 1970. Current Support is under Contract AT(ll-l)-21l8 with the above agency. 510. Vf ACKNOWLEDGEMENT The conceptual design of the Taxicrinic Processor of the Illiac III Computer System is largely the ^rork of three individuals; Roger E. Wieger, Bruce H. McCormick and the author. Dr. R. M. Lansford emphasized the importance of the associative addressing scheme -wherein the processor can automatically enter the Segment Name Table for additional "base de- scriptors, as needed. This facility, central to an effective Operating System, has been incorporated into the design of the Taxicrinic Processor. Familiarity with the Illiac III Reference Manual, Volumes 1, 2, and k 9 edited by B. H. McCormick and B. J. Nordmann, Jr., 1971 » is assumed. Bruce H. McCormick and John P. O'Donnell assisted in the edit- ing of this volume of the TP Manual. Thanks are also due to Mrs. Roberta Andre* and Mrs. Judy Arter for their labor on the many revisions of this volume and to Stan Zundo and the countless other members of the drafting department who sweated blood over the drawings and flow charts. Finally, a special thanks goes to Dennis Reed and his magical ITEK machine for the laborious task of the reduction and printing of the flow charts without which this manual would have been impossible. k. CONTROL SEQUENCES FOR THE BASIC MACHINE k.l Main Control U.l.l Summary of Instruction Formats k. 1.1.1 Primitive Instruction Formats k. 1.1.2 Imprimitive Instruction Formats ^.1.1.3 Operand Phrases U.1.2 Main Control Sequence k. 1.2.1 Main Control Sequence Description U.l.2.2 MAIN Control Logic U.1.3 Primitive Sequence h. 1.3.1 Primitive Sequence Description k. 1.3.2 PRIMITIVE Control Logic k.l.k Final Control Sequence 4.1.i+.l Final Control Sequence Description U.1.U.2 FINAL Control Logic 4.2 Memory Access 4.2.1 Modes of Memory Acces.s 4.2.1.1 Contiguous/Partitioned Storage Organization if. 2. 1.2 , Memory Sequence Entry Points 4.2.2 Constituent Tasks of Memory Access 4.2.2.1 Cell Alignment Check 14.2.2.2 . Base Register Check 4.2.2.3 Address Bounds Check 4. 2. 2. 3.1 Address Bounds Check - Functional Description 4.2.2.3.2 Address Bounds Check - Logic Description 4.2.2.4 Access Privilege Bits 4.2.2.5 Partitioned Mode Address Construction 4.2.2.6 Read/Write Byte Generation 4.2.3 Memory Access Sequence 4.2.3.1 Memory Access Sequence Description 4.2.3.2 Initial Address Construction Control Logic 4.2.3.3 QUEUE COUNTER UPDATE Control Logic 4.2.3.4 PARTITIONED MODE ADDRESS CONVERSION Control Logic 4.2.3.5 Memory READ Sequence Control Logic 4.2.3.6 Memory WRITE Sequence Control Logic 4.2.3.7 Memory Access Interrupt Sequence Description J+.3 Pointer Stack Operations i+. 3- 1 Available Space Sequences U.3.1.1 Available Space Sequence Descriptions k, 3.1.2 AS GET Control Logic U.3.I.3 AS RESTORE Control Logic ^.3.2 Pointer Stack Sequences ^•3.2.1 Pointer Stack Sequence Descriptions k. 3,2.2 STACK PR Control Logic U.3.2.3 UNSTACK PR Control Logic U.U Phrase Processin, £ U.U.I Phrase Process Sequence U.U. 1.1 Phrase Process Sequence Description U.U.I. 2 PHRASE PROCESS Control Logic U.U.2 Phrase Operation Sequence U.U.2.1 Phrase Operation Sequence Description U.U.2. 2 Phrase Operation .Control Logic U.U.3 Post-Operation Sequence U.U.3.1 '"Jst-Operation Sequence Description U.U.3. 2 POST-OP Control Logic U.U.U Increment ICT Sequence U. U.U.I Increment ICT Sequence Description U.U.U. 2 INCR ICT Control Logic U.U. 5 IBR Reload Sequence k.k. 5.1 IBR Reload Sequence Description U.U. 5-2 IBR RELOAD Control Logic U.U.6 Exchange PR-SBR Sequence k.k. 6.1 Exchange PR-SBR Sequence Description U.U.6. 2 Exchange PR-SBR Control Logic k. 5 Operand Stack Operations 4.5.1 Basic OS Sequences U. 5 • 1. 1 Basic OS Sequence Descriptions 4. 5-1.2 OS ENTRY Control Logic 4.5-1.3 SCR MOD Control Logic U-.5.1.U OS READ Control Logic U.5.1.5 OS WRITE Control Logic 4.5-2 Supplementary OS Sequences 4.5-2.1 Supplementary OS Sequence Descriptions 4.5.2.2 OS CLEAR Control Logic 4.5.2.3 OS INITIALIZE Control Logic k.6 Interrupt Sequencing k. 6.1 Local Interrupts k.6. 1.1 Local Interrupt Design Philosophy U. 6.1. 2 Interrupt Storage Segment k.6. 1.3 Interrupt Sequence ^4. 6. 1.3.1 Interrupt Sequence Description k.6, 1.3. 2 Interrupt Status Collection Logic k.6.1.k Increment and Check Sequence k.6.1.k.l Increment and Check Sequence Description k.6. 1.5 Interrupt Return Sequence k.6.1.5 .1 Interrupt Return Sequence Description 1+.6.1.5.2 Interrupt Status Restoration Logic H.6.1.6 AS Core 'GET Sequence k. 6. 1.6.1 AS Core GET Sequence Description U.6.1.7 AS Core Restore Sequence k. 6. 1.7.1 AS Core Restore Sequence Description U;6.1.8 SLEEP Sequence k. 6.1. 8.1 SLEEP Sequence Description k. 7 Display Console and Manual Intervention U.7 .1 General Philosophy U.7.2 Engineering Console Commands to the TP U.7.2.I Set Instruction Halt U.7.2.2 Reset Instruction Halt k.1.2.3 Set Maintenance Halt k.l.2.k Reset Maintenance Halt k.l. 2. 5 Set Sequence Halt h.7.2.6 Reset Sequence Halt U.7.2.7 Execute Sequence k.l .2.8 Interrupt U.7.2.9 Interrupt Return U.7.2.10 Run ^.7.2.11 Load/Read Registers k.l. 2. 12 Autoload U.7.2.13 Position H.7.3 TP -Engineering Console Interface - Logical Design ^.7.3.1 Engineering Console Command Decoding U.7.3.2 Engineering Console Command Execution U.8 Turn-On and Initialization k . 8 . 1 Power Turn On U.8.2 Register Clearing ^.8.3 TP Hardware Initialization U.8.U TP System Initialization if. A CONTROL POINT LOGICAL DESIGN if.A.l Design of the Control Point if. A. 2 The Use of Standard Control Points: if. A. 3 The Use of Calling Control Points if. A. if The Design of Control Sequences Using Control Points k. Control Sequences for the Basic Machine This section and the one following describe the control sequences used in the Taxicrinic Processors. Section k will he devoted to describ- ing the sequences and logic used in the "basic machine". This includes all those sequences used to control the basic TP operations concerned with the Operand Stack, Pointer Registers, etc. It also includes the logic for handling interrupts, console processor commands, and the start- up process. However, it does not contain any of the TP instruction sequences themselves. These will be described in Section 5 which is contained in Volume III of the Taxicrinic Processor Manual. The basic machine is essentially a distillation of all the sequences commonly used by a variety of TP instructions. These sequences operate in much the same manner as subroutines in that, when needed, they are "called" by some higher sequence. The general philosophy behind this process as well as a description of the specific logic used to implement these calls is given in Appendix ^+.A at the end of this section. Section k of the manual is divided into subsections on the basis of functional grouping of sequences. These groups consist of the Main Control sequences, the Memory sequences, the Pointer Stack sequences, the Phrase Processing sequences, the Operand Stack sequences, the Interrupt sequences, the Display Console control logic and the Initialization and turn-on logic. 8/20^71 Section 1+ - 1/1 U.l Main Control The Main Control logic supervises the basic instruction fetch procedure . It handles the decoding of the next instruction and then chooses the proper sequence for processing it. 12/18/69 Section k.l - 1/1 U.l.l Summary of Instruction Formats Every Illiac III instruction can be considered to be in prefix form: an operation (specified by a mnemonic byte) followed by operands (designated by operand phrases), if any. An instruction "with n operands in main storage has n operand phrases respectively, each one implicitly specifying the data address of the operand. In addition, an instruction may call upon operands from the Operand Stack. In this case, the operand address is implied by the mnemonic byte. The general format for the Illiac III instructions is shown in figure '+.1.1. a ,□, n ,□, □ v . j mnemonic operand phrase(s), mask, etc. byte Figure l+.l.l Illiac III Instruction Format This format consists of a single mnemonic byte normally followed by one or more operand phrases. These phrases may be long or short (see Section 2.1.2). In primitive instructions the total length of these operand phrases may not exceed k bytes. Some few primitive instructions, while adhering to the U-byte constraint, have fields with alternate interpre- tation: mask, etc. In imprimative instructions there may be up to 12 operand phrases. Here however, no restriction is placed upon the number of phrases which may be long. Operand phrases provide a uniform technique throughout Illiac III for addressing main storage and for operating on the 15 1 For imprimative instructions up to 12 operand phrases are allowed (3b bytes max. ) . 6/11/71 Section i+.l.l - 1/2 pointer stacks. In an operand phrase, the file (main store) address of an operand is implied "by giving the name of its associated pointer stack. That is, the data address is specified by the topmost pointer in the pointer stack named "by the operand phrase tag field. In addition to naming a pointer stack, an operand phrase may also specify operations which modify the value of the pointer and/or change the depth of the pointer stack. These operations take place before, after, or both before and after the actual execution of the instruction. 6/11/71 Section U.l.l 2/2 h. 1.1.1 Primitive Instruction Format Primitives correspond to the "machine language" of most other computer systems and are by far the most prevalent instruction- type. Primitive instructions always "begin with a single-byte phrase, the mnemonic phrase, which serves to name the instruction and to identify the number and format of any following associated phrase(s) since they are employed to construct the address (es) of operand cell(s). Other terminating phrases, such as counts or masks are also possible and are discussed in detail in later sections. 12/18/69 Section k. 1.1.1 - l/l U.l.1.2 Im-primitive Instruction Formats These are machine-oriented instructions, reducible without programmed intervention to a nested sequence of imprimitive and > primitive instructions, and ultimately to a sequence of primitive instructions. Imprimitives operate only on the pointer registers: renaming, storing, and modifying them. This class of instructions is also used to accomplish transfers of control, both conditional and unconditional. Imprimitive instructions always begin with a mnemonic byte. As is appropriate for the particular instruction, none or more operand phrases may follow the mnemonic byte. The length of each operand phrase (l or 3 bytes) is specified;: by the flag of the first byte of the phrase: a flag of '0' indicates \ a short phrase; a flag of '1' indicates a long phrase. The terminal phrase is specified by the low order bit of this same byte: ' 0' if more phrases follow, ' l' for the terminal phrase. Accordingly, the instruction field is consecutively partitioned into phrases until : a terminal bit is sensed (imprimitives). 771 Section U.l.1.2 - l/l U.l.1.3 Operand Phrases Every operand, other than those in the top of the Operand Stack, is designated "by use of an Operand Phrase. The length of each operand phrase (l or 3 "bytes) is specified by the flag of the first byte in each phrase: a flag of '0' indicates a short phrase; a flag of ' 1' indicates a long phrase. The fields of the two types of operand phrases are shown in Figure U.l.1.3. SHORT PHRASE: 0, TAG S i|l| j i i I i i i__i Modification Operation LONG PHRASE TAG FIELD SLASH OPERATION INDIRECT BIT LAST BIT FLAG MODIFIER F TAG S I L M Q , *— , • _l Figure U.l.1.3 Operand Phrase Format 6/11/71 Section U.l.1.3 1/1 4.1.2 Main Control Sequence 4. 1.2.1 Main Control Sequence Description The Main Control Sequence supervises all of the other sequences in the machine. It loads the mnemonic register with the instruction code, decodes the instruction, and establishes the instruction sequence (Section 5) which must be performed. In addition, the Main Control Sequence detects interrupts, executes and any other exceptional activities which may occur. The Main Control Sequence factors into 2 distinct parts: the Primitive Sequence and the Imprimitive Sequence, both terminated by a common Final Control Sequence (see Figure 4.1.2.1/1). Depending on the type of instruction, one of these first two sequences is called to decode and determine the execution of the instruction under consideration. The overwhelming majority of the instructions executed by the TP are Primitive Instructions, whose sequences are described in Sections 5.1-5.4. The Imprimitive Instruction Sequence is described in Section 5.5. The first task of the Main Control Sequence when a new instruc- tion is to be executed is to load the IR from the Instruction Buffer Register. Since every instruction ends by making sure that the IBR con- tains at least one byte of the next instruction, the IR is guaranteed to contain at least the mnemonic byte. The IR is loaded so that the instruc- tion's mnemonic byte is in the rightmost byte position and the remaining bytes are in sequence beginning at the left. This format is shown in Figure 4. 1.2. 1/2. After the IR has been loaded, the mnemonic byte is gated to the mnemonic byte register where it is stored for the rest of the instruction execution sequence. The mnemonic byte register is used to drive most of the control signals for the instruction sequences. The output of the mnemoni' register is automatically decoded to give the various instruction type codes (zero operand, one operand, imprimitive, PAU, Arithmetic, etc.) as well as the actual activating signal for the instructions themselves. The decoding network decodes the flag and first 6 bits of the mnemonic byte into 128 3/12/71 Section 4.1.2.1 - 1/4 output lines. These are then combined with the last two bits, if, necessary, to produce the instruction activation signals. This method was chosen since many of the instructions in fact use the last two bits as number type or cell size designators and therefore, these bits do not always have to be decoded to determine the instruction. Figure k. 1.3.2/1 gives the operation codes for all of the TP in- structions organized according to type. The next step is to check the instruction for legality. If the op-code does not represent a legal instruction, an illegal instruction interrupt is performed. If a privileged instruction is attempted while the TP is in slave mode, a privilege violation interrupt is executed. The high order two bits and the flag of the mnemonic are also decoded and either the Primitive or Imprimitive Sequence is started. Observe that the "se three bits identify the unit which will ultimately execute the instruction: TP, AU, PAU, etc. The beginning of the Main Control Sequence is shown in the flowchart at the end of this section. The rest of this section of the manual is devoted to describing the constituent . parts of the Main Control Sequence. Section U.1.3 starts by describing the Primitive Sequence. Section k.l.k describes the Final Control Sequence used for the termination of both primitive and imprimitive instructions. 6/23/71 Section k. 1.2.1 - 2/4 NAL TROL JENCE *""* z r» *• o S ° c/> A ~5 z o H-l h- Ul O Ul UJ u 1 > o > UJ 3 o IT o cc z 1 *"" ' ^ »- z UJ o z H UJ IMIT QUEI RIMI QUE UJ tr uj Q. UJ 3 o Ul 3 w < 1 Q. c/> 2 0) 1— I ~w CO _J o cr CL / \ r / \ — 1 \ \ »* i- . CO z H — • rs o cc w o 8 is z ^ CO ~ o o t— « tr < Q. d3aoo3a onv U3ddna oinoki3nw ^ Ul o •H o 1-1 H O fn -P C o o PJ •H O bO •H Q g H H H a] • H 0) •rH [in 6/11/71 Section k. 1.2.1 -3/i 1 1 Operand Phrase Mnemonic Primitive Instruction Left Justified on Byte 1 of Instruction Figure h. 1.2. 1/2 - Format for Instructions in IR 8/19/71 Section k. 1.2.1 - k/k / MAIN ( CONTROL I SEQ. '' CSA = IMM OPANDF = OSC = PROMOD = OPJ/E := 1 IR := IBR(lCT) MN := IR NO /PRIVILEGE" VIOLATION NO ILI := 1 YES PW := 1 ~t SPECIAL \ NO INSTRUCTION. DR := PR(O) SBR := DR YES MAIN Control Sequence U.l.2.2 Main Control Logic Control point MNT1 is used to load the IR from the IBR and to load the mnemonic byte register from the IR. Then a check is made for an illegal opcode or the attempted use of a privileged instruc- tion. In the former case, the indicator SILI/S. is turned on, while in the later, SPW/S is activated before control is given to the inter- rupt sequence. The signals SPCI/E, PAUI/E, ZEOP/E, ARTH/E and IMPI/E steer control to one of five sequences for further processing. In designing the logic necessary to make decisions regarding the above signals, it was tacitly assumed that they were mutually exclusive events (ZEOP/E and ARTH/E were combined into one signal). 8/19/71 Section U.l.2.2 - 1/1 MNT1 MNT2 BIR/G = 1 BRSBP/G = 1 IBR/S = 1 irmn/g = 1 OPJ/E = 1 RCSA/S = 1 RIMM/S = 1 ROPAM/S = 1 ROSC/S = 1 rprom/s = 1 ICNASS OR\ YES 'PVI = 1 and v YES PROT = YES YES YES s ZEOP/E YES MNTU bdr/g = 1 PRP/G = 1 i' MNT5 DBPR/G = 1 DRP/G = 1 SBR/S = 1 WSBV/E = 1 SILI/S = 1 MNT2 SPW/S = 1 MNT3 SCSS/S = 1 MNT3 SNCS/S = 1 YES Main Control Sequence U.1.3 Primitive Sequence The Primitive Sequence is the initial sequence used to process all primitive instructions. The basic purposes of this sequence are: 1) to ensure that the IR is loaded with the operand phrases before the instruction is executed, 2) to perform the required phrase operations as they are needed, 3) to place the initial byte of each phrase in a standard format in the IR after the phrase opera- tions have been performed, and modifiers are no longer needed, k) to take care of various contingencies such as modi- fication of PR#13 or conditional subtraction failure before instruction execution begins. The following sections give a detailed description of the operation and the control logic of the Primitive Sequence. In Section k. 1.3.1 the operation will be described in two distinct phases in order to separate out the effects of interrupts. The reason for this is that in this sequence the interrupt returns become rather confusing. 8/5/69 Section U.1.3 - 1/1 h. 1.3.1 Primitive Sequence Description Once the Main Control Sequence has determined that the instruction to he executed is a Primitive Instruction, the Primitive Sequence's first task is to determine whether or not the complete instruction is in the IR. This can he done "by knowing where the ICT is "pointing" in the IBR and how long the instruction is. The length is determined by the instruction type (i.e. how many operands) and whether the operands are long or short . If the IR must be refilled, the ICT is first incremented hy one. This enables the IR to be loaded without the mnemonic byte. In the case of a two operand instruction with one long phrase, this is extremely important since otherwise the IR cannot contain all of the phrase data. After the ICT is incremented it is checked once again to see if the IBR really needs to be reloaded or if it is only necessary to reload the IR from the IBR. When the IR (and possibly the IBR) has been reloaded the ICT must be restored to its original value so that any operations involving PR#0 are given the correct PR#0 value. This is done by incrementing the ICT by 7 and resetting the ICT overflow bit (there is no subtraction on the ICT). Next, the phrase processing operations are performed. For the one operand phrase instruction this is very straightforward. The first operand phrase is processed hy the Phrase Process Sequence as soon as the IBR and IR are loaded and the phrase is then finished. For the three operand phrase instruction, the sequence is fairly reasonable since each phrase must be short. After the first phrase has been processed, the IR is permuted left by one byte and the second phrase is processed by repeating the phrase sequence. The third phrase is handled in the same manner, after which the IR is returned to the format shown in Figure 4.1.3.1/1 The two operand phrase primitive instructions present a slightly more difficult problem. After the first phrase has been processed with the phrase process sequence, the first two bytes after the mnemonic are checked to see if the first phrase of the two phrase instruction is short. If it is, the same sequence that is used for the 8/19/71 Section 4.1.3.1 - 1/k three operand phrase instructions can be used, except that the phrase processing sequence for the third phrase is skipped and the IR is rotated one extra byte after the second phrase has been processed. At the end of this sequence the IR will have the format shown in Figure k. 1.3. 1/2. If the first of the two operands in the instruction is long, we must perform a certain amount of shifting in the IR before the second phrase can be processed. Note the format of the IR at this point (see Figure k. 1.3. 1/3). In order to arrange the IR so that the second phrase can be processed, the third byte of the IR (the leftmost byte, 2a) is gated into the first byte position (i.e. where lb originally was located). Note that this destroys the modifier portion of the first phrase. However, since this has already been processed, it does not matter any- more. The IR format now conforms to Figure k. 1.3. 1/2 except that the leftmost 2 bytes contain garbage. Once the IR is in this format it can be processed using the same procedure that is used for two operand phrase instructions with the first phrase short. If PR#13 has been modified by the phrase sequence, the OS will have been cleared out and OSC set to 1. Before the instruction execution can begin the OS must therefore be initialized. If there was a conditional subtraction failure, CSF is set to 1 and PR#0 is reloaded with its original value which was stored in the value portion of the SBR by the Main Control Sequence. Otherwise, CSA is checked to see if any conditional subtractions were attempted. If CSA = 1, a successful subtraction occurred and the CSF indicator is set to 0. If no conditional subtraction was attempted CSF is left alone. Finally, if the instruction has an immediate address option and it is specified, the field designator bits must be interpreted in terms of PL, PV, PR or SN instead of cell size. Then control is given to the sequence specified by the decoded mnemonic byte in the IR. 8 / 1 9/Tl Section h. 1.3.1 - 2/1+ .1st -phrase v2nd phrase phrase byte byte 1 byte 2 byte 3 Figure k. 1.3.1/1 Format of IR at End of Primitive Sequence with Three Short Phrases .1st phrase T_2nd phrase ^2nd phrase .2nd phrase byte byte 1 byte 2 byte 3 Figure k. 1.3.1/2 Format of IR at End of Primitive Sequence if Second Phrase is Lon£ phrase , 1st phrase , 1st phrase x.2nd phrase byte byte 1 byte 2 byte 3 Figure *» 1.3.1/3 Format of IR After the First Phrase is Processed if the First Phrase is Long 8/19/71 Section k. 1.3.1 - 3/U The treatment of interrupts in this sequence becomes fairly- complicated. This is due to the fact that because of the many phrase modifications, the sequence is not restartable from the beginning if an interrupt occurs in the middle of the sequence. In fact, there are three possible interrupt return restarting points. If an interrupt occurs in either the IBR Reload or the first Phrase Process. Sequence, the complete instruction can be 'restarted. If an interrupt occurs in second Phrase Process Sequence, the interrupt must return to the point immediately preceeding it and attempt to per- form it again when the situation has been fixed. If an interrupt occurs in the third Phrase Sequence, the interrupt must eventually return and repeat that sequence. Finally, if an interrupt occurs dur- ing the OS Initialize Sequence, the interrupt will return to the point just before the decision to initialize the OS. This point is also used as the normal interrupt return point for most interrupts which may occur during the execution of the Primitive Instructions. 8/19/71 Section 4.1.3.1 - k/k YES ICT := ICT+1 YES YKS YES YES YES := 1 DR := IR IK := DR MERG := 1 GO TO IBR RELOAD IR := IBR(lCT) ICT := ICT+7 ICTOV := INTERRUPT KG L* CALL: INTERRUPT SEQUENCE YES PLC2 = 1 IR — IR INHIBIT BYTES 0,2,3 YES CALL : INTERRUPT SEQUENCE CALL: PHRASE SEQUENCE CALL: PHRASE SEQUENCE PLC1 := 1 DR := IR IR := DR PLC1 DR IR := 1 := IR := DR YES CALL: INTERRUPT SEQUENCE PLC3 := 1 DR := IR IR := DR CALL: PHRASE SEQUENCE YES YES Primitive Sequence PRIMITIVE Instruct. SEQ. ENTRY B YES < ' CSF : = 1 OPANDF = LR = SBR pr(o) V = LR 1 i CSF := on return YES OSC := CALL: OS INIT on return YES SOSC/S := 1 CALL: INTERRUPT SEQUENCE SET CELL SIZE ACCORDING TO FD BITS Primitive Sequence Flow Chart Section 1+. 1.3.1 P. 2/2 k. 1.3.2 PRIMITIVE Control Logic The control logic for the Primitive Instruction Control Sequence is fairly complicated. As can be seen in the flowchart at the end of this section there are several signals "which must be decoded directly from the mnemonic byte itself. These include. 1) No operand phrase instruction, ZEOP/E 2) One operand phrase instruction, ONOP/E 3) Two operand phrase instruction, TWOP/E M "Complex" instruction, CXOP/E Fig. ^.1.3,2/1 shows a listing of all mnemonic phrases used and how they are categorized according to this scheme. The signals which indicate the state of the ICT are easily derived from the ICT bit signals using the standard decoder shown in Figure h. 1.3. 2/2. The sequence begins by activating control point PIT1. This control point is used as a "null" control point to generate the initial starting signal of the sequence. Note that if it were not present there would be an initial decision, based on the state of RLIBR, as to which control point to activate :PIT2, PIT3 , or PIT9. However, if PIMSTRT, the Primitive Sequence start signal, were used to activate this decision and PIT2 or PIT3 were chosen as a result, the ICTl/E signal would be activated. This signal causes an incrementa- tion of the ICT which in turn might cause a change in state in RLIBR. If PINSTRT is still on when this change occurs (and this is true in the general case) then PIT9 will also be turned on much earlier than it would have any right to be. In order to prevent this, PIT1 is used to generate an advance out signal which will stay active long enough to select the proper control point but which will also turn off way before RLIBR changes state. 6/11/71 Section k. 1.3.2. - l/l2 ZERO OPERAND INSTRUCTION CODES " Flag MN 1 MN 2 MNEMONIC BIT: INSTRUCTION MNEMONIC BIT: INSTRUCTION 3 h 5 6 7 8 3 h 5 6 T 8 ZERO (B) 10 SLUFF (B) 1 ZERO (H) 10 1 SLUFF (H) 10 ZERO (w) 10 10 SLUFF (w) 11 ZERO (D) 10 11 SLUFF (D) 10 ONE (B) 10 10 DUP (B) 10 1 ONE (H) 10 10 1 DUP (H) 110 ONE (w) 10 110 DUP (w) 111 ONE (D) 10 111 DUP (D) 10 COUNT (B) 10 10 XCH (B) 10 1 COUNT (H) 10 10 1 XCH (H) 10 10 COUNT (w) 10 10 10 XCH (w) 1 1 1 COUNT (D) 10 10 11 XCH (D) o o i a. o o BIT (B) 10 110 CPRL (B) 1 J. 1 BIT (H) 10 110 1 CPRL (H) 1110 BIT (w) 10 1110 CPRL (w) 1111 BIT (D) 10 1111 CPRL (D) 10 AND (B) 110 NOT (B) 10 1 AND (H) 110 1 NOT (H) 10 10 AND (w) 110 10 NOT (w) 10 11 AND (D) 110 11 NOT (D) 10 10 OR (B) 110 10 ACTP (#0) 10 10 1 OR (H) 110 10 1 ACTP (#1) 10 110 OR (w) 110 110 ACTP (#2) 10 111 OR (D) 110 111 ACTP (#3) 1 1 XOR (B) 1110 INRT 1 1 1 XOR (H) 1110 1 ': 1 l o XOR (w) 1 1 1 J- LTR 110 11 XOR (D) 1110 11 STR 1110 EQV (B) 11110 SVC 1110 1 EQV (H) , 11110 1 SVR 11110 EQV (w) 111110 11111 EQV (D) . 111111 WHO Figure 4.1.3.2/1 Instruction Mnemonic Codes 6/11/71 Section 4.1.3.2 - 2/12 1 ONE OPERAND INSTRUCTION CODES - Flag MN 1 MN 2 MNEMONIC BIT: INSTRUCTION 'MNEMONIC BIT: INSTRUCTION 3 k 5 6 7 8 3 k 5 6 7.8 PUSH (B) 10 LS (B) 3. PUSH (H) 10 1 LS (H) 10 PUSH (w) 10 10 LS (w) 11 PUSH (D) 10 11 10 LD (B) 10 10 RS (B) 10 1 LD (H) 10 10 1 RS (H) 110 LD (w) 10 110 RS (w) 111 LD (D) 10 111 1 POP (B) 10 10 10 1 POP (H) 10 10 1 10 10 POP (w) 10 10 10 10 11 POP (D) 10 10 11 110 ST (B) 10 110 J. 1 1 ST (H) 10 110 1 1 1 1 ST (w) 10 1110 1111 ST (D) 10 1111 10 SET (B) 110 10 1 SET (H) 110 1 .1 1 SET (W) 110 10 10 11 SET (D) 110 11 10 10 RESET (B) 110 10 1 J 1 RESET (H) 110 10 1 10 110 RESET (w) 110 110 1 1 1 1 RESET (D) 110 111 1 .1 TEST (B) 1110 1 1 1 TEST (H) 1110 1 1 1 C 1 TEST (w) 1110 10 1 1 1 1 TEST (D) 1110 11 1110 TESTM (B) 11110 SLEEP 1110 1 TESTM (H) 11110 1 INCK 1 1 1 1 TESTM (w) 111110 SIM 11111 TESTM (D) . 111111 Figure k. 1.3. 2/1 continued Instruction Mnemonic Codes 12/31/70 Section 4.1.3.2 - 3/12 PRESENTLY UNUSED INSTRUCTION CODES - Flag MN 1 MN 2 MNEMONIC BIT: 3 h 5 6 7 8 INSTRUCTION MNEMONIC BIT: 3 h 5 6 7 8 INSTRUCTION OOOOOO 1 10 11 10 10 1 10 10 10 11 10 10 1 110 111 ' 10 10 10 10 1 10 110 10 111 10 1 .1 10 10 10 11 1 3. 10 10 1 10 10 10 10 10 11 110 110 1 1 1 1 1111 10 110 10 110 1 1 1 1 3. 10 1111 10 10 1 10 10 10 13. 110 110 1 110 10 110 11 1 1 10 10 3. 10 110 10 111 110 10 110 10 1 110 110 110 111 110 3. 1 1 C I 1 C 1 110 3.1 1110 1110 1 1 1 1 1 1110 11 • 1 1 1 1 1 1 1 11110 11111 11110 11110 1 111110 111111 Figure k. 1.3. 2/1 continued Instruction Mnemonic Codes 6/11/71 Section k. 1.3. 2-4/12 Oil PRESENTLY UNUSED INSTRUCTION CODES - Flag MN 1 MN 2 MNEMONIC BIT: 3 h 5 6 7 8 INSTRUCTION MNEMONIC BIT: 3 h 5 6 T 8 INSTRUCTION OOOOOO 1 10 11 10 10 1 10 10 10 11 10 10 1 110 111 10 10 10 10 1 10 110 10 111 10 10 1 10 10 10 11 10 10 10 10 1 10 10 10 10 10 11 110 110 1 1110 1111 10 110 10 110 1 10 1110 10 1111 10 10 1 10 10 10 11 110 110 1 110 10 110 11 1 10 10 10 1 10 110 10 111 110 10 110 10 1 110 110 110 111 110 1 1 ] 1 1 Q 1 1 10 11 1110 1110 1 1110 10 1110 11 I 1 1 ('11101 11110 111 .1 1 11110 11110 1 111110 111111 Figure k. 1.3. 2/1 *ontinued Instruction Mnemonic Codes 6/1VT1 Section 14.1.3.2-5 10 u CD ft O O MISC. INSTRUCTION CODES - Flag MN 1 MN 2 MNEMONIC BIT: 3 k 5 6 7 8 INSTRUCTION MNEMONIC BIT: 3 h 5 6 7 8 INSTRUCTION 1 10 11 ASSIGN ASSIGN ASSIGN ASSIGN 10 10 1 10 10 10 11 PUSHF PUSHF PUSHF PUSHF (B) (H) (w) (D) 10 10 1 110 111 POPF POPF POPF POPF (B) (H) (w) (D) 10 10 10 10 1 10 110 10 111 PUSHFR PUSHFR PUSHFR PUSHFR (B) (H) (w) (D) 10 10 1 10 10 10 11 POPFR POPFR POPFR POPFR (B) (H) (w) (D) 10 10 10 10 1 10 10 10 10 10 11 SCAN SCAN SCAN SCAN (B) (H) (w) (D) 110 110 1 1110 1111 PACK RNAM UNPACK LINK 10 110 10 110 1 10 1110 1 1 1 1 1 SCANM SCANM SCANM SCANM (B) (H) (w) (D) 10 10 1 1 1 1 J 1 CALL EXECUTE GOTO EXIT 110 110 1 1 1 1 110 11 MOVE TRANS EDIT 10 10 1 1 I 10 110 10 111 NOP SPECIFY LOC 110 10 110 10 1 110 110 110 111 IF IFN 110 110 0]. : 10 10 110 11 RESU 1 1 1 1110 1 1110 10 1110 11 .1 110 1110 1 11110 11111 11110 11110 1 111110 111111 Figure h. 1.3. 2/1 continued Instruction Mnemonic Codes 6/11/71 Section 14.1.3.2 - 6/12 ZERO AND ONE OPERAND INSTRUCTION CODES - Flag MN 1 MN 2 j MNEMONIC BIT: 3 h 5 6 T 8 INSTRUCTION MNEMONIC BIT: 3 1+5678 INSTRUCTION 1 10 11 LIBR SL SIO HIO 10 10 1 10 10 10 11 RDCLK STT1M RDTIM 10 10 1 110 111 SR 10 10 10 10 1 10 110 10 111 10 10 1 10 10 3 11 GET 10 10 10 10 1 10 10 10 10 10 11 110 110 1 11 1 1111 PUT 10 110 10 110 1 10 1110 10 1111 10 10 1 1 1 10 1 1 INCL . 110 110 1 110 10 110 11 1 1 10 10 1 10 110 10 111 INCR 110 10 110 10 1 110 110 110 111 110 110 3. C I 10 10 110 11 DECL 1110 1110 1 1110 10 1110 11 1110 1110 1 11110 11111 DECR 11110 11110 1 111110 111111 one operand zero operand - Figure k. 1.3.2/1 continued Instruction Mnemonic Codes 2/25/71 Section U.l.3.2 - 7/12 1 ARITHMETIC OPERATION CODES - Flag MN 1 MN 2 MNEMONIC BIT: INSTRUCTION MNEMONIC BIT: INSTRUCTION 3 1+5678 3 1+5678 10 ADD (SFX) 1 10 1 ADD (LFX) 10 10 10 ADD (FLT) 11 10 11 ADD (DEC) 10 CVL (SFX) 10 10 10 1 NOP 10 10 1 110 CVL (FLT) 10 110 111 CVL (DEC) 10 111 10 CVF (SFX) 10 10 SUB (SFX) 10 1 CVF (LEX) 10 10 1 SUB (LFX) 10 10 NOP 10 10 10 SUB (FLT) 1 1 1 CVF (DEC) 10 10 11 SUB (DEC) 1 1 CVD (SFX) 10 110 CPRA (SFX) 110 1 1110 CVD CVD (lex) (FLT) 10 110 1 10 1110 CPRA CPRA (LFX) (FLT) 1111 NOP 10 1111 CPRA (DEC) 10 NEG (SFX) 110 MPY (SFX) 10 1 NEG ■(LFX) 110 1 MPY (LFX) 10 10 NEG (FLT) 110 10 MPY (FLT) 10 11 NEG (DEC) 110 11 MPY (DEC) 10 10 ABS (SFX) 110 10 POLY (SFX) 10 10 1 ABS (LFX) 1 1 1 1 POLY (LFX) 10 110 ABS (FLT) 110 110 POLY (FLT) 1 1 1 1 ABS (DEC) 110 111 POLY (DEC) 110 MNS (SFX) 1110 DIV (SFX) 110 1 MNS (LFX) 1110 1 DIV (LFX) I 10 10 MNS (FLT) 1110 10 DIV (FLT) 110 11 MNS (DEC) 1110 11 DIV (DEC) 1 1 1 ' TA (SFX) 11110 1110 1 TA (LFX) 111101 . 11110 TA {FLT) 111110 11111 TA (DEC) 111111 Figure k, 1.3. 2/1 continued Instruction Mnemonic Codes 1/27/71 Section U.l.3.2 - 8/12 Ill PAU INSTRUCTION CODES Flag MN 1 MN 2 MNEMONIC BIT: 3 h 5 6 T 8 INSTRUCTION MNEMONIC BIT: 3 k 5 6 7 8 INSTRUCTION OOOOOO 1 10 11 RESTART RESUME BOOLE SETORG 10 10 1 10 10 10 11 AREA LIST LISTSZ LISTLZ 10 10 1 110 111 10 10 10 10 1 10 110 10 111 REPLICATE RDERLZ WRITLZ WRERLZ 10 10 1 10 10 10 11 GATEIA 10 10 10 10 1 10 10 10 10 10 11 TESTP TESTB LISTI ERASEP 110 110 1 1 1 1 1 1 1 1 10 110 10 110 1 10 1110 10 1111 SHIFT TALLY TALLYHO CONNECT 10 10 1 1 10 1 1 1 LOADB PUSHB STOREB POPB 110 110 1 110 10 110,011 CLEARP SETP MOVEB READLZ 10 10 10 10 1 1 1 1 CJ ] 111 110 10 110 10 1 110 110 110 111 PLOT PLOTSZ PLOTLZ PLOTI 110 110 0]. ] 10 10 j 10 11 1110 1110 1 1 1 1 1 1 1 1 2. 1 COPY COPYC PLAND PLOR 1110 1 110 1 11110 1 1 .1 1 ] TOPOLOGY TOPOLOGY TOPOLOGY TOPOLOGY 11110 11110 1 111110 111111 PLMND PLNOR PLEXOR PLEQV Figure 4.1.3.2/1 continued Instruction Mnemonic Codes 3/16/71 Section 4.1.3.2- ICTI > >i > ICTEQ7 ICT2 > > ICT3 > > > ICTEQ6 Jo 1CTEQ6 > > ICTEQ5 ICTEQ5 ~-r> ICTEQ4 > ICTEQO Figure U.l.3.2/2 ICT Decoder 10/22/69 Section U. 1.3.2 -10/12 After control point PIT1, a decoding network is needed to determine if the I BR must be reloaded. The decision structure is shown in the flowchart at the end of Section U. 1 . 3 • 2 and the logic used to implement this structure is shown in Figure k. 1.3. 2/3. Note that since time is not important for this circuit, a minimum logic design was used even though it takes k collector delays. Control point PIT2 and the string of control points PIT1+ through PIT8 constitute another interesting situation. If an interrupt occurs during the call by PIT2 to the IBR Reload sequence, it is still necessary to restore the ICT to its original value. It is necessary, therefore, to save the outcome of the IBR Reload sequence by setting a flip-flop. If PIT3 is selected instead of PIT2 , the flip-flop must be reset so that no interrupt return is made. The actual decision is made following control point PIT8. PITH, PIT12, and PIT13 constitute a loop which may be executed twice if a three operand phrase instruction is being processed, A flip-flop, which is initially reset by control point PIT9 , is used to direct the flow of control during the execution of the loop. If the instruction is a three operand one, then, after the first execution of the loop control point PITlU is activated. This control point is not shown in the control point flow chart at the end of this section since all it does is set the control flip-flop. As soon as this is done control is returned to the beginning of the loop. After the second execution control is given to control point PIT15. During the execution of the loop, an interrupt may occur in the Phrase Sequence. If so, the control flip-flop is used to select which Interrupt Sequence entry point to activate. Eventually, when the interrupt has been taken care of and control is returned via one of the two interrupt return points, the control flip-flop must be set to its original state right before the interrupt was detected. 8/25/69 Section k. 1.3-2 - 11/12 ICTEQ7 ICTEQ6 ONOP/E TR9" ICTEQ5 TRl8 twop/e ICTEQ4 >n > > >tO > RLIBR Figure k. 1.3. 2/3 Circuit to Determine Reloading of IBR During Prim. Inst . Sequence 10/30/69 Section U.l.3.2 - 12/12 NULL PIT1 PIT2 PIT2 YES ICTl/E = 1 MERG = 1 MNEM = CALL : IBE RELOAD PIA011+ TWOP/E=l\ MOA d (IBR9 or; PIT3 PIT3 ICTl/E = 1 BIR/G = 1 BRSBP/G = 1 IBR/S = 1 pit6 PIT5 pisq/gi 31-2 ICT2/E = 1 ■* ICT2/E = 1 ,, Yllk ICT2/E = 1 PIA06 PIT9 31-3 PIT8 CALL: PHRASE SEQUENCE PIT7 RICTOV = 1 RPH3/S = 1 ICTl/E = 1 on return PITlU CALL: INTERRUPT ■ NCE ii YES PITIO •"TWOP/E \^YES ^and IBR9= 1 . PISQG2 BIR/G = 1 BIRO/N = 1 BIR2/N = 1 BIR3/N = 1 IRP/G = 1 PLC2 = 1 PIT13b PISQU SPH3/S = 1 I ENTRY B ) Primitive Instruction Sequence - Initial Control Sequence Control Step Flow Chart Section U.l.3-2 P. 1/2 PI S < '•'■ bdr/g = 1 IRP/C = 1 PLC1 = 1 PITH BIR/G = 1 DRP/G = 1 PIT12 on return CALL: PHRASE SEQUENCE PITll+c CALL: INTERRUPT SEQUENCE PIT13 on return PISQ1+ PIT15 BDR/G = 1 IRP/G = 1 31-4 31-5 PISQG2 PIA015 YES PLC3 = 1 PIT15x PLC2 = 1 1 ' PIT16 BIR/G = 1 DRP/G = 1 PIT18 DBPR/G = 1 LRP/G = 1 wprv/e = 1 PIT17 BLR/G = 1 pep/g = 1 ropanf/s = 1 SBR/S = 1 SCSF/S = 1 PIT19 RCSF/S = 1 on return PIT22 PIT20 SOSC/S = 1 CALL: INTERRUPT SEQUENCE YES ROSC/S = 1 CALL : OSINIT YES PIT21 IRTGO/G = 1 SCSS/S = 1 CALL: INTERHUPT SEQUENCE PIA021 on return Primitive Instruction Sequence - Initial Control Sequence Control Step Flow Chart Section 4.1.3.2 P. 2/2 U.l.U Final Control Sequence After the execution of an instruction sequence, control is given to the Final Control Sequence. During this sequence the post execution "pops" are performed on the operand phrases, if necessary, and the instruction counter is incremented. At this time various checks are made for PR#0 modification, changes in the operand stack pointer, an empty instruction "buffer register, interrupt conditions, or the end of an execute instruction. After all of these conditions have been examined, and taken care of if necessary, control is given to the beginning of the Main Control Sequence and a new instruction cycle begins . The following sections will give a detailed description of the operation and the control logic for the Final Control Sequence. In Section 4.1.U.1 the operation will be described in two distinct phases, just as in the Primitive sequence, so that the effects of the interrupts may be described separately. This will hopefully make the sequence operation less confusing. 8/5/69 Section k.l.k - l/l U.l.U.l Final Control Sequence Description The Final Control Sequence has two entry points, entry A which is the normal entry point for primitive instructions and entry B which is used to skip around the operand phrase post-operations and the incrementing of the instruction counter. This latter entry point is used by the Imprimitive instructions. The first 'part of the sequence utilizes the same logic used in the Primitive Sequence to classify the instruction as to the number of operands it has. This information is then used to determine how much to increment the ICT in order to point to the next instruction. Note how- ever that the post-slash operations are performed on all the operand phrases before the ICT is incremented. This insures that a proper value is obtained if PR#0 is used in an operand phrase and is popped. If PROM0D = 1 the ICT is not incremented. Care must be taken when using PR#0 as an operand phrase which is to be modified or popped. In order to ensure predicable results the following facts should be considered: 1) PR#0 is incremented after instruction execution and after all the operand post-slash operations have been performed. 2) If PR#0 is used in a primitive operand phrase and is modi- fied by the phrase operation or the instruction itself, PROM0D will be set to 1 by the time the final control sequence begins. 3) If a pre - and post-slash are both specified on PR#0 when it is used as an operand in a primitive instruc- tion, PROM0D will be set to after the post-slash has been executed. h) If a post-slash on PR#0 is specified by a primitive instruc- tion operand phrase with no pre-slash, PROM0D is set to 1 after execution of the post-slash. 8/5/69 Section U.l.U.l - 1/2 After the ICT has been incremented entry B joins the sequence. A check is made of OSC. If it is "l" the OS has been cleared during the execution of the primitive instruction and the stack must be reinitialized. If PROMOD = 1, then PR#0 has been modified during the instruction and the next instruction will not occur in sequence. Therefore a memory access to the new address must be made and the IBR loaded with the instruction at this point. The IBR will also have to be reloaded if the ICT = since this means that the instruction buffer is empty. Next the DR is loaded with the contents of PR#0 and PROMOD and OSC are reset to zero after which a check is made for any external interrupts which may have occurred since the last time an external interrupt check was made. Finally bit 9 of the DR is checked to see if an EXECUTE instruction is being processed. If so, return is made to entry B of the Imprimitive Sequence. Otherwise, the control begins again at the Main Control Entry. As in the Primitive sequence the treatment of inter- rupts in the Final Control sequence is complicated by the fact that the sequence is not necessarily restartable if an interrupt occurs in one of the sequences called by the sequence. There are actually four possible interrupt return starting points, labeled E, F, G, and H. If an interrupt occurs during the operation of the POST OP 0, 1 or 2 sequences the interrupt must return to interrupt return points E, F or G respectively. This is because once a post-op sequence has been performed successfully it cannot be redone wihout screwing everything up and since the old PR contents has been destroyed, there is no way to undo it. If an interrupt occurs during the OS INITIALIZE sequence or the IBR RELOAD sequence the interrupt will return to interrupt return point I 6/19/69 Section k. 1.4.1 - 2/2 CALL: POST-OP on return yes CALL: INTERRUPT SEQUENCE on return yes ITWO:»0 no /^COMPLEX \ yes CALL: POST-OP 1 on return yes CALL: INTERRUPT SEQUENCE I on return CALL: POST-OP 2 on return yes CALL: INTERRUPT SEQUENCE yes ICT:=ICT + 1 ITWO:=l ICT:=ICT + 2 yes yes yes yes on return FINAL CONTROL Sequence Flow Chart yes [ ENTRY j ICT:= ICT + 2 CALL: INCr. ict on return Section U.l.A.l -1/2 yes OSC:=0 CALL: OS INITIALIZE on return on return INTERRUPT SEQUENCE CALL: IBR RELOAD on return DR:-PR(0) OSC:»0 PROMOD:=0 yes yes CALL: INTERRUPT SEQUENCE on return FINAL CONTROL Sequence Flow Chart Section kj- .U.l - 2/2 U.1.U.2 FINAL Control Logic The Final Control sequence completes the execution of the in- struction and tests for interrupts and the completion of EXECUTE instruc- tions. The decision logic which appears after control points FCT3, FCTU and FCT5 is fairly complex. As can be noted from the flow charts, these control points can possibly activate control points FCT2, FCT6, FCTT, FCT12, FCT13 ,or FCTl^. Figure U.l.U.2/1 lists in boolean form the functions which will activate each of these control points. The FCAO signals shown indicate the Advance Out, A , signal from the correspond- ing control points. 8/20/71 Section U.1.U.2 - 1/2 FCT2: FCA01 • OPO • OPC v FCA05 V FCA03 • OP1 0P2 V • PROMOD( FCAOU • OP1 • 0P2 v OP2(IBR9 • IBR18)) FCT6: FCA05 V FCA03 • OP1 V FCAOU • 0P2 . PROMOD • OP1 • IBR9 FCT7: FCA03 • OP1 V FCA01+ . 0P2 V FCA05 . PROMOD • OP1 • 0P2(IBR9 + IBR18) FCT12: ENTRYB . OSC V FCA016 . OSC V FCA03 • OSC • PROMOD • OP1 V FCAOU • OSC . PROMOD . 0P2 V ,FCA05 • OSC . PROMOD FCT13: ENTRYB • OSC V FCAOI6 • OSC V FCA03 • OSC • PROMOD • OP1 V FCAOU • OSC • PROMOD • 0P2 V FCA05 • OSC • PROMOD V FCA012 • (PROMOD v PROMOD • ICTEQ) FCTlU: ENTRYB • OSC V FCA016 » OSC V FCA03 • OSC • PROMOD • OP1 V FCAOU • OSC . PROMOD • 0P2 v FCA05 • OSC . PROMOD FCA012 . (PROMOD v PROMOD • ICTEQ ) v FCA013 • PROMOD • ICTEQ Figure U.l.U.2/1 Boolean Functions for Control Points FCT2 , FCT6, FCTT, FCT12 , FCT13 8/20/71 Section i+. 1. U. 2 - 2/2 NULL CONTROL POINT FCT1 POST-OP ENTRY FCT3 on return FCT3b INTERRUPT SEQUENCE FCTlb POST-OP 1 ENTRY FCTU on return FCT4b INTERRUPT SEQUENCE POST-OP 2 ENTRY FCT5 on return FCT5b CALL: INTERRUPT SEQUENCE FCT6 ICT2/E = 1 FCTT ICT2/E = 1 yes ICT/E = 1 ITWO = 1 CALL: INCR. ICT on ret urn . FINAL CONTROL Sequence Control Step Flow Chart Section U.l.lj.2 - 1/2 on return CALL: OS INITIALIZE FCT12 on return CALL: INTERRUPT SEQUENCE FCT12b CALL: IBR RELOAD ENTRY FCT13 on return yes yes yes BDR/G = 1 PRP/G = 1 ROSC/S = 1 RPROM/S = 1 FCTlL no , /externals, .interrupt/ >m i i v yes ' ' CALL: on r eturn INTER] SEQU 3UPT ENCE FCT15 FINAL CONTROL Sequence Control Step Flow Chart Section U.l.4.2 - 2/2 k.2 Memory Access The Memory Access Sequence is the most complicated basic sequence in the Taxicrinic Processor. The main task of the Memory Access Sequence is to obtain data. The data may be of the immediate type, in which case no access to core is necessary, or it may be non- immediate , in which case one or more accesses to core will be needed. If access to core is required, the given virtual address is automatically checked against the contents of the bounds field of the base register. The alignment of the cell with boundaries appropriate for the given cell size is also checked. The address in core is then con- structed relative to the base address. If the base information for the segment name being requested is not in one of the seven "active" base registers, the Memory Sequence will automatically access the Segment Name Table, load the proper base information into the least-used base register and continue with the access. There are two distinct memory organizations, both of which are hardware implemented. In the Contiguous Data Access Mode all memory accesses are made through the pointer registers directly to the user's file by means of the base information. The Partitioned Data Access Mode makes use of a page map (in memory) which is accessed first to identify the page in memory which is to be accessed. This procedure allows for a more flexible storage organization at the cost of a slower access time. Both the Segment Name Table and the segments themselves may be partitioned. 8/13/69 Section k.2 - l/l 4.2.1 Modes of Memory Access 4.2.1.1 Contiguous /Partitioned Storage Organization There are two types of memory organization in the Illiac III system: contiguous and partitioned As far as the user is concerned virtual memory is conceived as contiguous, independent of the selected mode of memory organization. In the Contiguous mode each segment is referenced by its base information contained in a "base register. This information consists of the page address of the first page in the segment, the length of the segment and the access privilege of the segment. Each page in the segment must be contiguous with the rest of the segment and all of the pages have the same access privilege. In the Partitioned mode the various pages of the segment do not have to be contiguous. Pages can be stored in distinct areas of memory (possibly units having different access times), with each page having its individual access privilege. The Partitioned mode provides several advantages in storage allocation: 1) It is much easier to find storage for large files since the files do not have to be contiguous. 2) There is never a need for a complex "garbage collection" of blocks of storage which have been discarded by various processes, since there is no need to try to combine them into the largest contiguous blocks possible. 3) If a file, at some time subsequent to its initial storage allocation, requests more space, it can be conveniently taken from any unassigned pages in storage. The basic idea behind the partitioned mode is to take more efficient advantage of storage by discarding the need for contiguous storage. To allow a file to maintain storage pages in an arbitrary number of places in memory (up to 256 pages) however, a strategy is 6/14/71 Section 4.2.1 - 1/4 required to keep track of these page locations. The memory access strategy should demand a minimum of effort on the programmer's part, and as little extra hardware and time overhead as possible. To these ends the following decisions were made: 1) The implementation of the Partitioned Mode of memory accessing will he completely in hardware. 2) File storage allocation will be done by the Operating System. The programmer need not worry about the mode of memory access unless he specifically desires to request one or the other modes of operation. To keep track of the pages in the segment , a page map xs used. This consists of two consecutive pages in memory which are set up by the Operating System when the user first requests storage alloca- tion. The map contains up to 256 half-words which specify the page addresses in actual storage of the user's virtual memory pages and for each page, its access mode. These l6-bit half-words are arranged in the order in which the user's pages appear in virtual memory. (See Figure ij-. 2.1.1). In Partitioned Mode the base information is used to indicate the location of the page map and its access mode. In common with the Contiguous Mode the bounds field of the base register is used to make sure the address is within the virtual memory assigned to the segment. Each time an access is desired, the control unit checks the first flag bit in the base register for a "l" to see if the Partitioned Mode is to be used. If it is, the page address field of the virtual address (or file address), i.e., the page address in the user's virtual memory, is converted to an address of a half-word in the page map. This half-word contains the address in actual memory of that particular page 2/28/69 Section U.2.1.1 - 2/k programmer' s virtual storage Data Access Mode Bit = B D base *~~ address \+-b B page map page map \ \ "base address h»-a\ \ \ \ . ^ a b c d e 1st pac 2nd pc! page map (consists half won programmer's actual programmer's actual storage for contigu- storage for parti- ous mode Access Privilege Bits t tioned mode Data Access Mode Bit = 1 Access Privilege Bits D D fi □ bR bounds = k address of first page in actual storage BR bounds = h address of first page of page map Partial Add virtual relative page addr addr on page Partial Add virtual relative page addr addr on page Contiguous Format Partitioned Format Figure 4.2.1.1 - Pictorial Comparison of Partitioned Mode vs. Contiguous Mode of Data Accessing Note: Virtual Addresses (those constructed by programmer) are the same. Only BR's are different and these should only be assigned by the Operating System. Pro- grammer will not know the difference. '771 Section 14.2.1.1 - 3A in the user's virtual storage. After its page location has been accessed,the complete address of the data desired can be obtained by combining the page address with the relative byte address on the page as given in the original virtual address. 6/lU/Tl Section k. 2.1.1 - h/k U.2.1.2 Memory Sequence Entry Points There are two possible entry points to the memory sequence, the Direct and the Modified entry. In the Direct entry the eventual address is determined "by the particular Pointer Register specified "by the TGR. This entry is used for most operands 'which are specified by Pointer Registers. The Modified Entry is used by internal sequences which need to "manufacture" their own addresses. It cannot have the immediate address option. In the case where the Modified Entry is used the DR must contain the constructed address and the selection of the PRSN register must have already been completed. A LOAD-type operation is a single entry-exit operation. When the exit is made, the required operand cell is found left-justified in the LR (in the case of a byte, halfword, or word) or it is in the LR and the DR (in the case of a double word). A STORE-type instruction is a dual entry-exit operation: The first entry is made for one of the two possible entry variants; the first exit is made back to the main control from the store sequencing when the address has been constructed and checked. At this point, the data cells to be stored are loaded into the LR (and the DR in the case of a double word), left justified. The second entry to the store sequencing is then done, and the data cell(s) are stored in the operand address as requested. At the second exit, the store operation is complete. U/8/69 Section U.2.1.2 - l/l 1*.2.2 Constituent Tasks of Memory Access The purpose of this section is to describe the various parts of the memory sequence in considerable detail. The detailed logical design 'will be given as well as its functional operation. The following section (section ^.2.3) will give a description of the entire memory sequence operational flow chart. The final section (section k.2.k) describes the control logic used in the memory sequence and its control point flow chart. 6/11/71 Section U.2.2 - l/l U.2.2.1 Cell Alignment Check The TP Memory sequence requires that all cells which are accessed in core he aligned in such a way that a cell of a given size does not cross any correspondingly sized boundary in core. Thus a double word cell must not cross a double word boundary in core, a word cell must not cross a word boundary in core, etc. This restriction greatly eases the burden which would fall on the TP if arbitrarily located cells had to be accommodated. Also since the two major data streams which would require arbitrary boundaries, i.e. the OS and the instruction stream, are automatically taken care of with double word buffers, there is no great hardship on the programmer. It is hoped that with the experience of the 360 systems programming, the problem of writing compilers and assemblers which will assign cells to their proper boundaries will not be too great. At any rate it is the responsibility of the memory sequence to check every access request to ensure that the cell is properly aligned. This is a simple matter since it only involves checking the cell size and the low order 3 bits of the address. This is done at the beginning of the, memory sequence before the segment name is compared with the association logic to see if the base information is in one of the BR's. The logic to detect a misaligned cell is shown in Figure k. 2,2. 3/1 • If a misalignment is discovered, an alignment check interrupt is generated. 6/11/71 Section k ' 2 ' 2 ' 1 - 1/2 DRB33 CSD DRB34 CSW DRB35 CSH >p[> > ALGN Figure k. 2. 2.1/1 Alignment Check Logic 8/17/71 Section 1+.2.2.1/1 - 2/2 H.2.2.2 Base Register Check At the "beginning of a memory access a check must be made that the necessary base information is present in one of the hardware base registers in the TP. This is done by the Association Logic described in connection with the Base Registers in Section 2.5«1-U. If no base register is found with the required base information, the Memory Sequence must access the Segment Name Table to obtain the base descriptor and then load this data into the base register which has been used least recently (see Section 2.5.1. 3 for a description of this selection process). It should be noted that the Segment Name Table may be partitioned and thus it may be necessary to go through a page table to get to the Segment Name Table. 6/II/71 Section k.2 .2.2 - l/l U.2.2.3 Address Bounds Check k. 2. 2. 3.1 Address Bounds Check - Functional Description The purpose of this logic is to examine all outgoing memory- addresses to insure that an address falls within the area allotted to the segment and hence, program, in question. An address is constructed using the base address and either a pointer value field (direct entry) or a preformed constant (modified entry). If the pointer value or constant passes a comparison with the given bounds for that segment, it can be added to the base address (the high order l6 bits of a 2k bit address) to give a final 2\ bit address which may then be sent to the core unit. (This is the procedure for a contiguous mode access; partitioned mode will be explained later in Section U.2. 2. 5). A graphical illustration of the process is given in Figure U.2.2.3 J- • The base registers hold a 2-byte (l6 bit) base PAGE ADDRESS and an associated 1-byte page count*, or BOUNDS. The page address indicates the beginning of the segment associated with the given base register. The BOUNDS is one less than the number of pages in the segment. This greatly simplifies checking the logic for a relative overflow (see below). The minimum allowed segment length is thus one page, corresponding to a BOUNDS = 0. The maximum is 256 pages (BOUNDS = 255). One page contains 256 bytes, Q\ words, or 32 double words. In the bounds check, the l6-bit virtual address is compared with the given BOUNDS to check for an "absolute" bounds overflow, i.e. the virtual address exceeds the page count . * Actually (page count) - 1; see text 6/11/71 Section U. 2.2. 3.1 ■ 1/3 J T POINTER VALUE: ', I L. I- — — T CONSTANT : ; ! ; : VIRTUAL ADDRESS: | j: (within segment) 031 174 23 031 197 DR COMPARE TO BOUNDS: 059 IF VALID, ADD BASE: fC. | 187 085 f / Oth byte contains bound: 8t is added with rest of BR toDR, but is ignored in AR ADDRESS : 187 II 6 197 ooo BASE fl ' (24 bitf (assumed) AR Note: This file is allowed 60 pages of storage beginning at For this example, the numbers in page 187 085 each byte are the decimal representation of the binary contents, i.e. they run from to 255- Figure k. 2.2. 3.1 - Address Bounds Check U/8/69 Section k. 2. 2. 3.1 >■■ 2, If this condition occurs, the hounds overflow indicator (B0V) is set and an interrupt may he initiated. As the actual hounds checking begins, the DR contains the virtual address while the DB holds the hounds. The BOUNDS hyte (which is the leftmost byte in the DB) and the page address byte of the virtual address (the second hyte from the right in the DR) are simul- taneously compared for DR > DB. If this does not occur the address is within hounds. If it does occur, an ahsolute overflow will take place. In the case where DR = DB there is no need to worry about a hounds overflow condition since cells heing accessed through the memory sequence are not allowed to cross double word boundaries. Thus any cell which began in the last page assigned to the segment and extended over the boundary would be illegal simply because of improper cell alignment. For memory access in the Partitioned Mode the bounds check still works satisfactorily. In this case the bounds check method for the Con- tiguous Mode determines if the user is trying to exceed his allotted virtual storage. Since the user is not allowed to change his page map, there is no danger of the user straying into someone else ' s storage as long as he remains inside any one of his pages. At the same time, if the user tries to access data which overlaps a virtual page boundary, he will again be stopped because of improper cell alignment. 8/19/69 Section U.2.2.3.] - 3/3 4.2.2.3-2 Address Bounds Check-Logic Description The purpose of the address "bounds check logic is to rapidly check the 8 bit page number of the virtual address which will be accessed. against the 8 bit bounds which is contained in the base register bounds field. In order to do this rapidly, the comparison is done in parallel fashion without using the adder. The actual bounds checking logic is given in the TP Logic Book in Drawings 06-01 and 06-2. The eventual purpose of the logic is to set the BOVI (bounds overflow) flip-flop if this is necessary. This flip-flop is composed of cross-connected NAM) ' s on 2^0-00 cards, as shown in Figure k. 2. 2. 3- 2/1. When not in use the input signals to this flip-flop rest at "l". Initially the flip-flop can be reset by setting the reset system signal, RSYS, to "0' At the beginning of the bounds checking operation, BDCK/E goes to "0" and BDCK/E goes to "l" (the timing is not important in this case). Since BDCK/E is common to every input circuit in the checking logic this effectively begins the checking operation. At this time the DR contains the address to be checked while the DB contains the bounds and the base address. In particular bits 19 through 26 of the DR contain the page portion of the address, while bits 1 through 8 of the DB contain the bounds. In order to set the flip-flop properly the logic in Drawing 06-1 is used to generate the BGT signal, which if off indicates that the number represented by the DR bits is greater than the number represented by the DB bits. The logical equation for this signal is as follows: BGT = DB (1) • DR (19) v DB (2) * DR (20) • l(2) v .«- v DB(8) • DR (26) • 1(8) where 1(2) = DB (1) • DR(19) 6/6/69 Section 4.2.2.3-2 - 1/ BOVI BOVI RSYS Figure h. 2. 2. 3. 2/1 Bounds Overflow Flip-flop Logic 8/17/71 Section U.2.2.3.2/1 - 2/6 I(i) = DB(i-l) • DR (18 + i-1) • I (i-l) l(2), i = 3, 1 *, — , 8 BGT = 1 if in some position i, DR (l8 + i) > DB (i) and l(i) = I(i) =1 if in some position, k < i, DB(k) > DR(l8 + k) The equation for BGT is somewhat complicated. The idea is to start at the highest order bit positions of the two numbers and scan down each position until one comes to a position in which the DR bit is a "1" and the DB bit is a "0". If at this point there is no higher order bit position with a DR bit of "0" and a DB bit of "l", then the DR is greater than the DB and BGT = 1. In order to keep track of what happened in the previous positions the l(i) signals are used. These signals indicate for each position, i, whether or not any previous position had a DB bit of "l" and a DR bit of "0". Some examples of the use of these equations are given below: DR < DB DR = 10110110 DB = 11010011 I = 1000000 BGT = 00000000 = DR > DB DR = 10110110 DB = 10011011 I = 1111000 BGT = 001 = = 1 8/19/69 Section U.2.2.3.2 - 3/6 Note in the first example that the first bit position to have a DR hit of 1 and a DB bit of is the third most significant bit position. However note that the second most significant bit position has already had a DB bit of 1 and a DR bit of so we need to ignore the third bit position and set BGT to 0. In the second example the third position is again the most sig- nificant position to have a DR bit of "l" and a DB bit of 0. This time, however, there is no higher order bit position with a DB bit of 1 and a DR bit of so that this time we want to set BGT to 1. But what happens if DR = DB? DR = DB: DR = 10110110 DB = 10110110 I = 1111111 BGT = 00000000 = In this case note that all the l(i)'s are 1. However since there is never any position with a DR of 1 and a DB of zero, the BGT signal is never set. At this point we have everything we need to generate BGT with logic. In actuality we will generate BGT by dot-oring eight NATO circuits, one for each bit position, and using these NATO's to check each bit position for a DR bit of 1 and a DB bit of 0. At the same time we also want to use the l(i) signals for each position to inhibit the NATO of its corresponding position if any previous position had a DR bit of and a DB bit of 1. This is what is represented by the previous equation for BGT and what is shown in Logic Drawing 06-1 of the TP Logic Book. The l(i) signals are all generated in parallel rather than recursively as shown in the equations. This allows a much faster circuit and does not add too much logic. The l(2) signal is the easiest since it only involves checking one previous position. The succeeding l(i) signals are generated using 2^1-00 circuits and a 23^-02 diode matrix board (see Figure U. 2.2.3.2/2) . 6/6/69 Section 4.2.2.3.2 - 4/6 IM CM > — > O Z> OV CO of CO CL 2* r- co CD ][ 1 ! r t t ! [ 3 ! -3 ■ m N !! ] [ ! r t ! ! ' X > EXCHANGE CONTROL BYTE ON RETURN DR PAR := 1 BR(6) := DR i«. BR WITH QUEUE CT.^ Memory Sequence - Initial Address Construction Section 4.2.3.1 P. 1/5 CYCT := CYCT + 1 QCNT(i) = QCNT(i)+l FOR ALL i QCNT(i) = QCNT(i) + 1 for i< Selected Counter QCNT(i) := QCNT(i) + 1 FOR ALL i CYCT = CYCT + 1 YES QCNTOV(i) = FOR ALL i QCNT(i) = FOR i = Selected Counter ( DOME j Memory Sequence - Queue Counter Update Sequence Section U.2.3.1 P. 2/5 PART. MODE. ( ADDRESS ) CONVERSION' AR LR save LR LR := DR INHIB. BYTES 0,1 DR := LR LS/E := 1 (DR-»LR) PLC3 IB38/E IBCO = 1 = 1 = 1 ICIBC1 = 1 DR = LR RS 1 byte inhibit low order bit and AR := LR 0,1 bytes on reply from XN LR := AR DB : = BR (PRSNR(TGR) AR := DR+DB restore LR on data return CD := AR GENERATE READ/WRITE AND EXCHANGE CONTROL BYTE LS 1 bit LJOP = 1 DR = CT IBC2 = 1 IBC3 = 1 PLC3 := 1 LR : = PRSNR(15) MERGE DR— LR INHIB. BYTE 2 YES YES [(MEMORY | . INTERRUPT/ ^\SEQ. DR := AR PLC3 = 1 AR := LR LR := DR ( RETURN j Memory Sequence - Partitioned Mode Address Conversion Section 4.2.3-1 IBC2 := 1 IBC3 := 1 YES PLC2 := 1 YES LR := PR(TGR) YES LR := PRSN(TGR) CD:= AR GENERATE READ /WRITE BYTE & EXCH. NET CONT.BYTE wait for data return LR := CT wait for data return DR := CT [OLD = I s * MEMORY \ YES ^MALFUNCTION,. ? READ 2NTRY FROMl INITIAL] -OPS.SEQ. RELEASE EXCHANGE NET Memory Sequence - Read Section U.2.3.1 P. V5 PR(TGR) := LR FLPR/N := 1 PR(TGR) y := LR FLPR/N := 1 PR(TGR) L := LR YES YES /REGISTER OPTION YES / VALUE OPTION YES / LINK OPTION PRSN(TGR) := LR CD := AR GENERATE READ /WRITE BYTE & EXCH. NET CONTROL BYTE WAIT FOR XN REPLY CD := LR YES YES NO CD := DR RELEASE XN Memory Sequence - Write Section U.2.3.1 P. 5/5 k. 2.3.2 INITIAL ADDRESS CONSTRUCTION Control Logic The Initial Operations sequence performs the initial address construction in the memory sequence and checks for the various possible non-hardware interrupts. Referring to logic drawings 36-la through 36—3 | the only non-straightforward part of the logic is the MT3-MTH-MT5 comple which is used to check for the presence of the desired base information, and the MT10-MT11 complex which accesses the exchange net. MT3 is actually a normal control point except for the fact tha the output of the delay circuit is not used to reset its flip-flop. Instead the Advance Out, A , is fed to one of two other delay circuits ; depending on whether or not the desired base information was present. At the same time one of two task signals is turned on to perform the desired operations. The outputs from the two delay circuits are or'ed together and fed back to be AND'ed with the GODELY signal and eventually to reset the flip-flop in control point MT3. Thus the overall affect is to first activate the association ; logic for the base registers using MT3. Then when this causes the DA and NYET signals to be valid the choice between control points MT^- and MT5 can be made. Note that in either case it is still necessary for the task signals turned on by MT3 to remain on while MTU or MT5 is activated The MT10-MT11 complex might be called a hybrid calling control point. It is important to understand its operation since this type of logic will be used whenever the Exchange Net is accessed in order to get to core memory. The complex is a calling control point in that it makes; use of normal return and interrupt return signals. However, it also acts like a regular control point in that it uses a delay. To make matters even more confusing there are two task signals . The first task signal, MT10 , as shown in Figure U.2.3.2, is used to gate the AR to the cable drivers and activate the read/write byte generator. The delay circuit then waits a suitable length of time until the read/write byte is also present on the cable driver lines. Later on it may be possible to eliminate this delay if it turns out that ad/write byte generation can be done in parallel with the exchange net luest. 7/15/70 Section U.2.3.2 - 1/2 The second task, which begins after the delay has finished, generates the Exchange Net control byte and makes a request for the proper memory box. The control point then remains active until the return signal is activated. In this case the return signal will be the signal that the memory cycle has started. This signal will reset the two control task signals and either activate the next control point if no data error occurred, or generate an interrupt if there was one. If no reply is received from the exchange net, a timer (see logic drawing 37-2) will eventually run out and generate an Exchange Wet No Reply signal, XNNRP, which is sent to the interrupt return input to the calling control point. This will cause the control point to reset and turn off its task signals. At the same time, the no reply signal is also used to automatically activate the Memory Interrupt Sequence . Thus the I output of the Calling Control point need not be connected. This same technique is used if the memory or any other external unit does not reply to a TP request within some predetermined length of time (usually quite long relative to a single access of the particular unit) . 7/15/70 Section U.2.3.2 - 2/2 MT1; MM MTla STMF/S = 1 MSTOR i l\NO ( (RETURN ] MT13 brg/s = 1 DRP/G = 1 wrbp/e = 1 ■■■ l- s MT12 TP/G -= ] !•; = l C MT2a MT2b DUMMY CP MTlb edr/g = 1 ppp/g = 1 SNS/G = 1 tnb/g = 1 MT16 bdr/g = 1 prp/g = 1 psnprb/g= 1 PSNRR15 = 1 MT15 ASRW/E = 1 DRP/G = 1 MTlU BDR/G = 1 PRP/G = 1 PSNPRB/G= 1 SNRD/E = 1 MT11 enmcb/e = 1 DRP/G = 1 PLC2 = 1 PSNRW15=1 RIMF/S= 1 MT3 MT6 MT5 BRO/S = 1 ADD/E = 1 ADDO/N = 1 AMCK/E = 1 ararf/g= 1 bdck/e = 1 brg/s = 1 *Mf53T bdr/g = 1 PSNP/G= 1 MT7x YES STTRP/S= 1 YES YES MT7w YES STBOV/S = 1 MT8 YES SNAMT = 1 CALL: PART. MODE ADD. CONVER. MTIO ARP/G = 1 CDR/E = 1 RWBG/E = 1 on return if NO /INTERRUPT BRG/S = 1 SNRD/E = 1 MT7y STMNT/S = 1 MT7z STDNT/S = 1 Memory Sequence - Initial Operations - Control Step Flow Chart Section U.2.3-2 P. 1/2 ADD/E = 1 ADDO/N = 1 AMCK/E = 1 ARARF/G = 1 BDCK/E = 1 BRG/S = 1 BRSBP/G = 1 ( RETURN ) MTl»x QCTUSTRT = 1 mtU YES YES YES YES SGMKT/S - 1 MTlTx miTy SGDHT/S - 1 SGTRP/S » 1 MT17w SILAC/S = 1 MT17V SGBOV/S = 1 MT17Z SNAMT = 1 CALL: PART. MODE ADD. CONVER. MT18 Memory Sequence - Initial Operations - Control Step Flow Chart Section 4.2. 3.2 P. 2/2 k. 2.3-3 QUEUE COUNTER UPDATE Control Logic The Queue Counter Update sequence is used to update the status of the queue counters for the hardware base registers in the TP each time one of these registers is used. It is a fairly simple sequence. Two "null" control points are used (MT26 and MT29) in the counting loops. Since the control sequence is designed to work independently of all the other control logic once the sequence has been activated, there is no return signal generated at the end of the sequence. There is also no need to use a calling control point to start the sequence. It should be noted that if this sequence is activated with a task signal, the actual operation will not start until the task signal returns to its "steady state" of "l". 6/10/69 Section U.2.3.3 - l/j QUEUE. COUNTER ] UPDATE J ' SEQUENCE ' RCYCT/S = 1 MT21+ NO QCNT/E = 1 CYCT/E = 1 MT25 YES XQCNT/E = 1 MT27 NO YES 1 1 RQ0VF/S = = i 1 ' RSCTR/S = = i \ r QCNT/E = 1 CYCT/E = 1 MT28 MT30 MT31 MT26 NULL MT29 NULL Memory Sequence - Queue Counter Update Sequence Control Step Flow Chart Section 4.2.3.3 P. 1/1 U.2.3. h PARTITIONED MODE ADDRESS CONVERSION Control Logic The Partitioned Mode Address Conversion Sequence is used to access the page map in a Partitioned Mode access and construct the actual physical core address which will be needed to access core. At the same time it checks the access hits connected with the page map entry to he sure the access is a valid one. The sequence utilizes one control signal, SNAMT, and one internal control flip-flop, PMAREP. SNAMT, the Segment Name Table signal, is used to indicate that the sequence is being used to access a Segment Name Table entry. This information is important in determining which interrupt indicator to set ; if an interrupt condition occurs. PMAREP, the Partitioned Mode access repeat flip-flop, is. used to control the operation of the page map accessing loop. In the case of a virtual page overflow access in Partitioned Mode, the page map must be accessed twice, once for each page on which the data appears. During the second access PMAREP is set to one so that the flip-flop can be used i| to control several different operations in the second access of the page map. The MT37-MT38-MT39 control point complex is another example of the use of complex control points to generate the Exchange Net control signals. MT37 generates the proper read/write byte and then MT38 makes the request for service while MT37 is still on. After a response is obtained from the Exchange Net, MT39 will cause the LR to be gated to the AR unless the VPGOV flip-flop is on and it is the first access to the page map. When this is done, the control waits for the return signal from the core box indicating that the data is on the data lines waiting to be read. In MTUO the delay must be set long enough for the access mode checking logic to produce valid outputs so that the decision logic in front of MTUl will give the correct results. 6/11/69 Section U.2.3- 1 * - 1/2 Control Point MTUi is used to set any interrupt indicators if this becomes necessary. The logic in front of it is used to test the access mode of the page map entry which is, at that time, stored in the DR, left justified. If any interrupt condition occurs, MTUl is activated and the proper indicator is turned on according to what type of condition caused the interrupt. Note that the interrupt signal for the memory sequence as a whole is turned on after MT^l has set the proper indicator. This is done to save time and logic since there is no need to have a special Partitioned Access Mode sequence interrupt return when all it would do is activate the Memory Sequence interrupt return anyway. 6/11/69 Section U.2-3- 1 * - 2/2 MT32b MT32a MT33a MT33b 1 X1EI BAR/G = 1 LRP/G = 1 BLR/G = 1 DRP/G = 1 IBCO = 1 IBCl = 1 LDR/G = 1 LS/E = 1 RREP/S = 1 MT37 MT36 MT 35 ii m3h ■ ' ARP/G = 1 CDR/E = 1 RWBG/E = 1 PGMPAC = 1 ADD/E = 1 ADDO/II = 1 BRG/S = 1 SWRD/E = 1 ARP/G = 1 BLR/G = 1 bdr/g = lrp/g = = 1 = 1 PLC3 = = 1 I on X 1 i i ■ 39 •eturn MTl+O : = 1 3 = 1 on BDR/G = 1 CTP/G=1 ■ IBC2 = 1 IBC3 = 1 IJOP/E = 1 ' data return ■ ' RY \ WO FAILURE YES SPAR/S = 1 MTte BLR/G = 1 PLC3 = 1 PRP/G = 1 psnprb/g = 1 PSNRR15 = 1 MTl+l-v SNAMT = l x STTRP/S = 1 MTl+lw SGTRP/S = 1 MT^Lx .YES 9 \YES SNAMT = 1 STPNT/S = 1 SILAC/S = 1 MT^ly SOPNT/S = 1 " MTl43 DLR/G = 1 DLR2/K = 1 11 mtUU ARP/G BDR/G 11 MTl+5 BAR/G = 1 LRP/G = 1 PLC 3 = 1 '' MTl)6 DLR/G = 1 Memory Sequence - Partitioned Mode Address Conversion Sequence Control Step Flow Chart Section 4.2.3.1+ H.2.3.5 Memory READ Sequen-ce Control Logic The Memory READ sequence is a somewhat unconventional sequence. In its most commonly used access it is not a sequence at all, hut merely an extension of the Initial Operations Sequence. In this case there is no activation of a calling control point and the read operation will "begin at either MU8 or M50 depending on whether an im mediate or normal access will he performed. There is one control signal for the READ access sequence, XNHOLD. If this signal is on the sequence will not release the Exchange net when it is finished. It is sometimes necessary, however, to call the Memory READ sequence as an actual sequence. In this case the calling control point will cause the activation of dummy control point M^9 which in turn activates M50. Rote that immediate address is not possible on a direct call to the Memory READ sequence. The purpose of the Immediate Address entry is to directly access the pointer register fields instead of making a core access if this option is specified hy the operand phrase. In this case the TGIM signal will he "l". If MSTOR = 0, i.e. a memory read, the main memory sequence, Initial Operations , will detect that an immediate read is to he performed and will directly activate M^8 of the READ sequence. In an immediate read access there are actually four possihle cases which may occur depending on the field designator hits (IR3^ and IR35). Six NATO's are used to decode these IR hits. At any given time during the memory sequence only one output from the logic will he "0". In all four cases the PRP/G, BLR/G, and TNB/G signals must he set to "l" to enahle the gate from the PR to the LR. In addition, if the field designator indicates a link variant (IR3U = 0, IR35 = l), the PLC2 signal, which causes the data to be permuted left 2 bytes, must be set to "l". Finally if the field designator is not a register or segment name variant (i.e. it is either a link or value) the right most two hytes into the LR must be inhibited by setting IB2/E and IB3/E to "l". 12/22/70 Section U.2.3.5 - 1/7 Once the proper PR field(s) is loaded into the LR , the READ sequence activates the main memory sequence return signal. Due to the nature of the timing requirements for the Exchange Net and the core memory units , the operation of the READ control logic for a conventional memory access is fairly complex, although the logic itself is fairly simple. The Exchange Net request made by complex control point M50-M51 is a typical example of the technique described in Section ^4.2.3.2. Referring to Figure U. 2. 3. 5/1, the first task signal in this type of complex: control point is used to gate the needed data and read/write byte to the cable drivers while the second task signal generates the control byte once this data is valid. The reply from the Exchange Net is used for the normal • return while the Exchange Net No Reply signal is used for the interrupt return. Since the Exchange Net-TP logic takes care of the interrupts in these cases, the Interrupt out signal from the control point is not connecte and is only used to reset the control point. '; The technique used to obtain the data from the memory units is I: somewhat unconventional. Since the memory units always send first the left half and then the right half of the double word accessed during the memory cycle , it is necessary for the control sequence to know which word it wants at any given time. The method used for obtaining data in a memory read is shown in Figure k. 2. 3. 5/2. After the Exchange Net has replied to the TP's processor request (complex control point M50-M51) , the memory control sequence has about 300 ns. before it must accept the data coming back from the memory units. During this wait the M52 control point is activated. When this control point is first activated the data will not be ready. It is importan in designing the control sequence to make sure that this control point is activated before the data has arrived from core since otherwise timing errors will result and incorrect data may be loaded into the TP register. The MT52 task signal will turn on the necessary gates to transmit the data from the Exchange Net cable terminators into the LR . These signals will remain on until the return input of the control point is activated. 1 2/22/70 Section lj.,2.3.5 - 2/7 i-o OZ Q. HO O l<° or a: l< O 10 a. UJ or u o a o •H ■s -p c > a Eh cd H o "-> X tr\ w • en CM 0) •H P>4 UJ o 2 < 2 > — a < 12/30/70 Section >k2.3°5 - 3/7 o UJ z < A to 10 z- ro I O I O Q£ a: i< o ro 10 CVJ l~° l<° £ ct: CVJ m l< IT) 2 Osl r- < Q. < o s 2 O <2 O m fl o •H P crt a fH O K M 01 ■H L0 P -. jt LINK OR VALUE OPTION PLC2 = 1 MTi*8y PSNPRB/G = 1 SNRD/E = 1 SMS/G = 1 MTU 8 BLR/G = 1 PRP/G = 1 TNB/G = 1 MTU8 DUMMY CP writ 9 AEP/G = 1 CDR/E = 1 RWBG/E = 1 MT50 BLR/G = 1 CTP/G = 1 WAIT FOR DATA FROM MEMORY MT52 MT53 BDR/G = 1 CTP/G = 1 WAIT FOR 2nd WORD FROM MEM YES XNREL = 1 MT5^ ENMCB/E = 1 MT51 YES NO Memory Sequence - Memory READ Control Point Flow Chart U.2.3.6 Memory frRITg Sequence Control Logic As in the case of the READ sequence, the WRITE sequence logic is somewhat unconventional. It is controlled by one control signal, XNHOLD and one control flip-flop, IMF. If XNHOLD is activated the sequence will not release the Exchange Net when it is finished. If IMF is set to 1, the WRITE sequence will perform an immediate access write. The purpose of an immediate access write is to store data in the pointer register fields of the PR indicated by the tag register instead of writing into core at the location specified by that PR. In this case the WRITE sequence will begin at M55 if the register, value, or link options have been specified or at M56 if the segment name option has been specified. In either case the data which is stored in the LR will be gated into the proper PR field(s). The actual gating in an immediate write depends on the option. If the register option is selected, both the link and value fields are gated. If the link or value options are used, there will only be a half- word of data left justified in the LR. In this case the respective field is gated but the flags are inhibited. In the value option the data must be permuted 2 bytes to the left. In all the link, value and register cases, the data is gated from the LR to the PR selected by the tag register. In the segment name option the halfword left justified in the LR is gated to the segment name register selected by the contents of the tag register. If the memory write access is not an immediate access the sequence will begin with complex control point M57-M58, which requests a path to the memory units from the Exchange Wet. Once an open path has been obtained, the WRITE sequence must immediately begin sending the data to be written. There are two time slots during which data is sent to the memory unit. If the address of the cell being written into begins in the second half of the double word, the data must be sent during the second time slot. Other- wise it must be sent during the first. Thus, in order to save logic, on any cell beginning in the second half of the double word, the contents of the LR are sent during both time slots. In all other cases, the LR is sent on the first time slice and the DR on the second time slice. This method works, mainly because the memory unit will ignore all unnecessary data information (based on the status of the Read/Write byte which was sent 12/22/70 Section h.2.3.6 - 1/2 when the Exchange Net was first accessed). The data is actually sent by the M59-M60 and M61-M62 complex control points. These complex control points are made up of standard control points plus extra delay logic. The delay elements within M59 and M6l are set to allow time for the data to be gated from the selected register to the cable drivers. The advance out signals are then used as MT60 and MT62 and are made to turn on the Til signal. The delay elements following these signals are set to keep the Til signal on long enough to satisfy the requirements of the memory unit. After both words of data have been sent, the WRITE sequence will release the Exchange Net provided that XNHOLD is not on. The sequen must wait for a return from the memory unit indicating that the data has been received. The Exchange Net-TP Interface logic generates the MURT signal for this purpose. The waiting is performed by a calling control point which uses MURT as the normal return and MUNRP, the memory unit no reply signal, as the interrupt signal. As in the Read Access logic the li interrupt out signal is not connected since the Exchange Net-TP Interface Logic will generate the interrupt if the memory unit does not respond within the specified time. After the memory unit has replied the ACFAIL line is checked tc see if there was a parity error in transmission or a memory unit malfunct;; If so, control is transferred to the Memory Interrupt Sequence. Otherwis, the sequence returns. 12/22/70 Section U.2.3.6 - 2/2 WPRL/E = 1 WPRV/E = 1 FLPR/N = 1 PLC2 = 1 WPRV/E = 1 MT55y FtPR/H = 1 WPRL/E = 1 MT55z YES DBPR/G = 1 LRP/G = 1 TNB/G = 1 MT55 SEGMENT NO NAME OPTION LRP/G = 1 SNS/G = 1 SNWT/E = 1 TNB/G = 1 MT56 TII/E = 1 MT60 CDR/E = 1 LRP/G = 1 MT59 ARF33 I 1 X N ° MT6ly LRP/G = 1 XNREL = 1 DRP/G = 1 MT6lx CDR/E = 1 MT6l TII/E = 1 MT62 YES Memory Sequence - Memory WRITE Control Point Flow Chart 4.2.3.7 Memory Access Interrupt Sequence Description The purpose of the Memory Access Interrupt Logic is to prepare the TP for a memory access interrupt return if any interrupt conditions are detected during the execution of the memory access sequence. The interrupt operations can he divided into two stages: setting the interrupt indicator logic, and saving the necessary interrupt information so that the interrupt processor will be able to determine what happened. The interrupt indicator is set at the time the interrupt is first detected by activating one of the special control lines used for this purpose. The table shown in Figure 4.2.3.7/1 lists the various interrupts which might occur and groups them into sets of temporally exclusive interrupts, i.e. interrupts which cannot be on at the same time. This allows them to be coded using a fewer number of bits than if each condition had its own indicator. The logic in Figure 4.2.3.7/2 depicts the design of the relevant part of the interrupt indicator logic and shows how the indicator setting signals in the memory sequence , are used to set it properly, according to the codes given in Figure 4.2.3.1 The process of saving the necessary interrupt information is som what different in the memory sequence than it is in the other TP sequences This is because in the case of the memory sequence, unlike the other TP sequences, the important interrupt information may be lost once the se- quence interrupt return is activated. Thus it becomes necessary for the memory sequence itself to save the interrupt information instead of waiting for the main interrupt sequence to do so. In particular, it must store the segment name and virtual address of the particular access which caused the interrupt. As a convenience to the calling sequence, it also leaves the virtual address in the DR before it returns. This, in many cases, allows the calling sequence to undo what it had previously done before the interrupt occurred, and thus "buck" the interrupt still further "upstairs". 6/11/71 Section 4.2.3.7 - l/ 14 1 2 3 k 5 l) Hardware /So ft ware Error Hardware Errors: 2-3) 00'- Memory Unit 01 - Arithmetic Unit 10 - Pattern Articulation Unit 11 - Interrupt Unit 4-5) 00 - No Interrupt 01 - Parity Error 10 - Unit Malfunction 11 - No Reply Software Errors : 2) Segment /Segment Name Table Error 3) Not There Interrupt /Other Interrupt Not There Other : 4-5) 00 - no interrupt 01 - Page Map 10 - Data 11 - Page 4-5) 00 - No Interrupt 01 - Bounds Overflow 10 - Trap 11 - Illegal Access Figure 4.2.3.7/I Arrangement of Interrupt Indicator for Memory Interrupts 8/19/71 Section 4.2.3.7 - 2/4 INI IN2 IN3 INU No Indicator 1 STBOV 1 STTRP 1 1 SILAC 1 No Indicator 1 1 STMNT 1 1 STDNT 1 1 1 STPNT 1 No Indicator 1 1 SGBOV 1 1 SGTRP 1 1 1 SILAC 1 1 No Indicator 1 1 1 SGMNT 1 1 1 SGDNT 1 1 1 1 SGPNT Figure U.2.3. /3 Indicator Codes for Memory Interrupts 6/16/71 Section U.2.3.7 -3/ 1 * There are actually three possible situations which may- occur when an interrupt situation is detected in the memory sequence. (a) If an interrupt is detected in the Partitioned Mode sequence, the AR will contain data which must eventually be stored in the LR before making an interrupt return, and the DR and LR will contain junk. (b) If an interrupt is detected in the Memory Write sequence, both the LR and DR will contain data which must be saved while the AR will contain junk. ' In this case, the DR is not to be loaded with the virtual address of the access (which would still be in PRSNR(l5)) since the DR may contain data which was to have been written into core. (c) In all other memory interrupt situations the AR and DR will contain unneeded information which must be saved. Thus the memory interrupt sequence is set up as follows: its main task is to construct a one word datum containing the segment name and the virtual address and store it in the interrupt storage memory. This can be most easily done using the merging options in the IR. Before this can be done, however, the current contents of the IR must be preserved. The natural place to do this is in the AR since, except for the Partitioned Mode case, it always contains junk and even in this one exception its contents are supposed to be transferred to the LR anyway, after which its data is no longer needed. In those cases where the DR must be loaded with the virtual address, this operation is performed before the merging takes place. A flowchart for the Memory Interrupt Sequence is given at the end of this section. 6/17/71 Section U.2.3.7 - h/k AR IR: DR: := IR = PRSNR(15) = PRSNR(15) PL2/E := 1 IB2/E := 1 IB3/E := 1 IR:=PRSNB(SNRS) INSM(O) := IR IR := AR INSCT=INSCT+1 Memory Sequence - Memory Interrupt Section k.2.3-1 P. 1/2 Entry / Entry \ v MT20b BAR/G = 1 IRP/G = 1 Entry " MT19 ARP/G = 1 BLR/G = 1 i' MT21b BIR/G = 1 PRP/G = 1 PSNPRB/G = 1 PSNKR15 = 1 ' r MT20a BAR/G = 1 IRP/G = 1 1 ' MT21a BDR/G BIR/G = 1 = 1 PSNRR15 = 1 psnp/g = 1 MT22 BIR/G = 1 IBC2 = 1 IBC3 = 1 PLC2 = 1 RINIP/S RINSB/S SNRD/E PSNP/G = 1 = 1 = 1 = 1 MT23a MT23b INSBW/E = 1 IRP/G = 1 ARP/G = 1 BIR/G = 1 INSCT/E = 1 Memory Sequence - Memory Interrupt Control Step Flow Chart Section P. 2/2 U.2.3.7 k. 3 Pointer Stack Operations The Pointer Stack operations, as stipulated by the slashing conventions (see Section U.U), are used during the processing of the various instructions. The format for the Pointer Stacks is shown in Figure k.3- Each cell consists of a double word which is subdivided LINK VALUE NAME not used Figure k.3 - Pointer Stack Format into h halfword fields. The first halfword is used for the link addre; to the next lowest entry in the stack. The second and third half words contain the Pointer Register value and segment name respectively, pre- serving the contents of the Pointer Register when this particular cell was pushed into the stack. These three halfwords are in the normal forft as used for a Pointer Register. The last halfword of the stack cell is< not used. The main Pointer Stack operations are STACK and UWSTACK. Thes operations are used respectively to "push" the current contents of a PR into its stack and to "pop" the top of a stack in core into its PR. To perform these operations it is also necessary to call available space sequences which get cells from available space as they are needed or return them when they are no longer needed. These sequences are called AS GET and AS RESTORE respectively. 3/5/69 Section k.3 - l/l U.3.1 Available Space Sequences k. 3.1.1 Available Space Sequence Descriptions The available space sequences control the use of the avail- able space both in Pointer Stack operations (where PR#lH is used) and in GET and PUT instructions where the program has declared one or more PR's to be in the available space format. The available space format is explained in Section 2.4.1.3. There are two available space sequences: AS GET and AS RESTORE. These sequences are called most frequently by the TP to manipulate pointer stacks. In these instances PR#l4 serves as the source of the LINK and COUNT quantities. For GET and PUT instructions, however, the TGR identifies the available space pointer. Thus there are two possible sources for the PR name: the TGR or the NPRlU/S signal which forces the selection of PR#l4 by the name bus. In the Available Space control logic this selection is made by a special flip-flop, ASTRS (Available Space Tag Register Select), which must be set (l for tag register, for PR#lU) before entry into the sequence. This flip-flop then controls the source for the name which appears on the name bus when an available space pointer register must be referenced. In the flowcharts the controlling pointer register is indicated by PR(NB) where it is understood that ASTRS will control what is on the name bus. The AS GET sequence is used to obtain a cell from the "free list" in the available space file. If the "free list" is empty the sequence will try to get the cell from the consecutive storage area. If this in turn is empty, an Available Space Empty interrupt is generated. If the AS GET sequence takes its cell from the "free list" ,it must use the link in the available space pointer register to access the 3/10/69 Section 4.3-1.1 - l/k top free list cell in order to find out what that cell is pointing to. This new link is then placed in the left half of the available space pointer register and the address of the previous top cell of the free list is -left in the DR (right justified) for use by the "calling sequence." If the free list is empty the cell will be taken from consecu- tive storage in one of two possible ways. If the cell is to be taken from PPjlU available space then the cell size is assumed to be a double word. In this case 8 is automatically added to the count. Before this is done, however, the old count is gated to the LR to be saved. If the available space PR is determined by the Tag Register (i.e. if ASTRS = l), then the cell size may be any number of even bytes up to 256. The exact number is contained in the first halfword of the segment. Thus in this case the DR is set to and then used to access this first halfword. On return from the memory sequence, the LR will contain this halfword integer, left-justi- fied. After gating it into the DR, right-justified, the DB can be loaded with the available space pointer register count and the cell size can be added to it. At the same time that the addition is being performed the LR can be loaded from the DB with the old count . Regardless of how the new count is obtained, it is stored in the DR. The next step is to make sure that the new beginning of the consecutive storage is still within the part of core allowed for the available space file. If it is not, then the cell we just obtained (its address is the old count) may not be entirely within bounds and an Avail- able Space Empty interrupt is made. The check for Available Space Empty is made by performing a bounds check on the new beginning address of the consecutive storage. If the check finds that the obtained cell is within bounds, the new count, which was stored in the DR, is loaded into the link and count fields of the Available Space PR. Then the LR, which has previously been used to store the old Available Space count field, is gated to the DR and the sequence returns. 8/U/69 Section k. 3.1.1 - 2/k To determine if the free list is empty, the link and count fields of the available space pointer register are compared to see if they are equal. If they are, the free list is empty. The logic used to make the comparison is shown in Figure ^.3.1.1. The flip-flop CONS is set to one whenever a cell is obtained from consecutive storage instead of the free list. This flip-flop may be used by sequences which call AS GET if it ever becomes necessary, due to an interrupt, to undo the effects of the AS GET sequence at some later point in the sequence which called it. Since any interrupt which originates within AS GET will occur before any permanent changes in the registers are made, no special operations are necessary to "undo" anything. The AS RESTORE sequence is used to return a cell to the available space free list. The l6-bit address of the cell to be returned is placed right-justified in the DR by the "calling sequence". The AS RESTORE sequence then accesses this cell and stores in it the link currently residing in the available space pointer register. It then takes the address of the cell being returned and stores it in the link of the available space PR. In summary the available space pointer register now points to the cell which was just added and that cell, in turn, points to the cell which was previously the top cell of the free list. Note that if an interrupt occurs in the AS RESTORE sequence during the address construction phase of the memory sequence, the DR is restored to its original value by the memory interrupt sequence before the interrupt return is performed. This enables whatever sequence called AS RESTORE to get rid of the cell ultimately. The detailed flowcharts for both of these sequences are at the end of this section. Figures k. 3. 2.1/1 through /3 of Section U.3.2.1 gives pictorial examples of Pointer Stack Operations which should help explain the operation of AS GET and AS RESTORE. 12/22/70 Section U.3.1.1 - 3A LKCTC/E DB35 DB?7 DB35 DBI7 DB34 DBl6 DB34 DBI6 DB20 DB2 DB20 DB2 DBI9 DB I DBI9 DBI i : d v_ J K. 29-1, 29-2 J 34-7 FIGURE 4.3.1.1 IC IMPLEMENTATION OF LINK-COUNT COMPARE 8/7/69 Section U.3.1.1 ~ k/k MSTOR := cell size = h call: MEMORY MODIFIED ENTRY PL2/E := 1 DR := PR(NB) PR(NB) :=LR ASTRS = 1 if tag register determines available space PR = if PR//11+ is used DB := PR(NB) CONS := ENABLE LINK COUNT COMPARE SET PRSN SEL. DB := DR := DB MSTOR := cell size = h call: MEMORY MODIFIED ENTRY PL2/E := 1 DR := LR DB := PR(TGR) LR := DB DB := BR(BNR) AR := DR + DB ENABLE BOUNDS CHECK CELL SIZE = B YES BOVT := ASE := 1 CONS = 1 PL2/E := 1 PR(NB) = DR PL2/E := PR(NB) := DR v DR := LR Pointer Stack Available Space Sequence Flow Charts AS GET Sequence Section U.^.l.l P. 1/2 LR:= DR SET PRSN SELECT LOGIC MSTOR := 1 CELL SIZE= H CALL". MEMORY MODIFIED ENTRY on return YES DR := LR LR := PR(NB) CALL : MEMORY WRITE on return YES PL2/E := 1 PR(NB) T := DR ASTRS = 1 if tag register determines available space PR = if PR#ll+ is used ( return] Pointer Stack Available Space Sequence Flow Charts AS RESTORE Sequence U.3.1.2 AS GET Control Logic The AS GET sequence obtains a cell from the available space list and returns the address of this cell in the DR right justified. The only control flip-flop is ASTRS, the Available Space Tag Register Select flip-flop, which is shared with the AS RESTORE control logic. It must be set to "0" if PR#1*+ is to be used to access the available space file and set to "l" if the file will be indicated by the PR whose name is in the tag register. The flip-flop controls which input is selected for the NAME BUS: TNB/G if ASTRS = 1 and NPRlU/S if ASTRS = 0. Most of the logic is fairly straightforward. AST2 is shared between two control steps in the AS GET sequence. Note that the cell size is controlled by using the direct con- trol lines. The desired line is held on during each memory access and during the addition. Thus no change is made in the status of the cell size flip-flops during the sequence. However, the Cell Size Selector is changed and must be changed back by the calling sequence if it is neces- sary to use some other selection. This same technique is used in the AS RESTORE sequence. When a new cell must be obtained from contiguous storage in the AS GET sequence, the 32-bit Adder is used to increment the count. Note that the inhibits are not turned on for the leftmost two bytes in the result. There is no real need to do this since when the new count is gated back to the available space PR, these two bytes will not be used. If this two byte addition produces an overflow, the resulting address will "wrap around" to the low end of the segment. This can cause problems since if the bounds overflow test were made on this new address, no violation would be detected. Thus after the addition, if an adder overflow is detected, an Available Space empty interrupt return is executed. 7/15/69 Section U. 3. 1.2 - 1/2 A minor problem can arise in using the bounds check on the new count to determine if there is space remaining in the Available Space segment: if the last cell ends exactly on the upper boundary, the bounds check of the new count will indicate an overflow even though there is, in fact, one cell left. This occurs because the bounds check logic checks the validity of the one byte cell beginning at the new address. In order to fix this it would only be necessary to subtract 1 from the count before checking its bounds. However, it was felt that this solution was more trouble than the fact that one cell might be wasted, so it was not used. 8A/69 Section U.3-1.2 - 2/2 BDR/G = 1 BLR/G = 1 LKCTC/E = 1 PLC2w 1 PRP/G = 1 RMSR/S = 1 SCSC/S = 1 SNS/G = 1 AST1 res ii AST1 NPRll^S = 1 AST6 AST2 AST5 BDR/G = 1 LRP/G = 1 PLC2 = 1 ON RETURN CCSH/E = 1 GO TO MEMORY PRE-INC. START BDR/G = 1 1 ' AST7Y BLR/G = 1 PRP/G = 1 TNB/G = 1 AST7 ADD/E = 1 V AST7X P8/E = 1 YES ASTIO RBOVIS = 1 SASE/S = 1 V YES AST8 NO ADR/G 1 r AST9 ADD/E = 1 BRG/S = 1 BRSBP /G = 1 AST11 TNB/G = 1 AST11 NPRlU/S = 1 AST11 DBPR/G = 1 DRP/G = 1 PLC2 = 1 WRPRL/E = 1 AST12a AST12b AST12b LDR/G = 1 SCONS/S = 1 DBPR/G = 1 DRP/G = 1 WRPRV/E = 1 TNB/G = 1 TNB/G = 1 AST1 ■lceq2i\ no AST2 CCSH/E ■ 1 GO TO MEM. PRE-INC. START ras XASTRS AST3 TNB/G = 1 YES 11 AST3 BDR/G - 1 PLC2 = 1 PRP/G = 1 NPRlU/S = 1 ASTU YES TNB/G = 1 NPRlU/S = 1 " ASTit DBPRG = 1 LRP/G = 1 RCONS/S = 1 WRPRL/E = 1 AST12b NPRII4/S = 1 Pointer Stack Available Space Get Sequence Control Step Flow Chart U.3.1.3 AS EESTORE Control Logic The AS RESTORE Control Sequence is used to return a cell, whose address is contained right-justified in the DR, to the free list of a given available space pointer register. It utilizes one control flip-flop, ASTRS, the Available Space Tag Register Select flip-flop, which is also used by the AS GET sequence. This flip-flop, if on, indicates that the TGR is to be used as the source for the name of the available space pointer register. If ASTRS = 0, PR#lU, the available space pointer register for the PR stacks, is used. The sequence itself is quite straightforward. 8A/69 Section U.3-1.3 - 1/1 ' INTERRUPT VRETURN AST17 CCSH/E = 1 CALL: MEMORY WRITE ASTRS 2 j\ li AST13 NPRllt/S = 1 YES/INTERHUPT YES ' ' AST15 LDR/G AST16 BLR/G = 1 PRP/G = 1 AST13 TNB/G = 1 i ' AST13 DLR/G = 1 SMSR/S = 1 SMS/G = 1 w ASTlU CCSH/E = 1 CALL: MEM. MODIFIED ENTRY TNB/G = 1 AST18 YES -*< ASTRS = 1 TNB/G = 1 AST16 NPRll»/S = 1 AST18 NPRlU/S = 1 AST18 DBPR/G = 1 DRP/G = 1 PLC 2 =1 WRPRL/E = 1 Pointer Stack Available Space Sequence AS RESTORE Control Step Flow Chart i+ . 3 • 2 Pointer Stack Sequences U.3.2.1 Pointer Stack Sequence Descriptions As described in Section 4.3.1, these sequences are used for stacking and unstacking pointer stacks. The STACK sequence, as shown in the flowchart at the end of this section, consists of first using AS GET to obtain an empty cell from available space. The l6-bit address of this cell is stored by AS GET right-justified in the DR. It should be noted that in this case, as in every case of an address (or link) being used from the pointer register available space file, the base register named by PR#l4 is used in addressing memory. Next the cell address in the DR is copied into the LR for storage while a memory write is initiated. If an interrupt occurs during the address construction phase of the memory sequence then the cell obtained by the AS GET sequence must be returned. This can be done without accessing core since that cell still contains the links which connect it with either the free list or consecutive storage. Thus if CONS = the cell was obtained from the free list and only the available space PR link field need be loaded with the address of the obtained cell in order to get it back on the free list . If CONS = 1 the cell was obtain* from consecutive storage and both fields of the available space PR will have to be loaded with the address of the obtained cell in order to put it back in consecutive storage. If there was no interrupt during the address construction phase of the memory sequence, then the STACK PR sequence continues by loading the DR (left- justified) with the segment name of the PR which is being stacked. Then the name is merged into the LR so that the segment name is in the left halfword of the LR and the address of the new cell being accessed is in the right halfword. Finally the LR is gated to the DR and then reloaded with the contents of the PR to be stacked. Control then 8/4/69 Section 4.3.2.1 - 1/5 returns to the memory sequence which writes the data into the cell obtained by AS GET. It should "be noted that a double word access is made when the PR information is being stacked. However, the three PR fields (link, value and segment name) take up only six bytes. This means that the last 2 bytes in the double word cell are filled with whatever happens to be in the right half of the DR. At the present time this is the address of the cell being accessed. This may or may not be of any use. Once the PR has been stacked, however, the data can be overwritten if desired. When the memory access has been completed, another check for ' interrupts must be made since there may have been a hardware error in writing the data into core. If there is an interrupt the same Available space pointer restorations as previously described are initiated. If not the PR which was stacked is updated by loading into its link field the address of the cell just stacked. This address is still located in the right half of the DR. After this has been done the STACK PR sequence returns . An example of a stack operation is shown pictorially in Figures k. 3. 2.1/1 and k. 3. 2. 1/2. The UWSTACK sequence is used to pop off the top cell of a pointer stack. The first step is to load the AR and DR with the pointer link, right- justified. The AR is then checked for zero, since if the link of the PR is zero, there is no more stack and we will not be able to do a pop. If the link is zero, a Stack Empty interrupt will occur. The next step is to check for a tag of 13. If the tag is 13, the OS must be initialized (if it has not already been so) and the OSC flip-flop must be set. Note that if the OS is cleared, the DR must be reloaded since its contents will have been destroyed during the clearing sequence. 8A/69 Section k. 3-2.1 - 2/5 PRN: \: VALUE PR 14: BEFORE 1° > V > .« I L ^ / ^ I — > K J prn: 5 VALUE L PRI41 4 8 ^ AFTER -L I .2 .3 .4 (A .' ! 7 l 6 ^ \_ _a j^ i^ _> .> FIGURE 4.3.2. 1/ 1 STACK WITH LINK * COUNT PRN: 3 VALUE ^ PRI4: 6 BEFORE J L "> 2 3 A 4 5 J L 7 8 9 J I L ^_A prn: o 6 VALUE PRI4: 7 7 V. k AFTER J L 2 3 4 5 6\ T\ A 8 I J L I * '* * JK -^ r FIGURE 4.3.2.1/2 STACK WITH LINK = COUNT 5/19/69 Section k. 3.2.1 - '-' After the check has heen made, the PR Segment Name Register Selector is set to PR#lU and a memory read is performed to obtain the contents of the second PR cell in the stack. This is then loaded into the PR and the cell just accessed is replaced on the free list using the AS RESTORE sequence. Note that after the memory cycle is over, the DR must again be loaded with the address of the cell to he restored. This must obviously be done before the PR is overwritten with the new contents. The DR content is used by the AS RESTORE sequence. If interrupts occur in either the OS CLEAR or memory sequences, a direct interrupt return can be performed since no changes have been made which would cause the sequence to be non-restart able. However, if an interrupt occurs in AS RESTORE, the contents of the PR will already have been changed to reflect the unstacking and thus this must be undone. The procedure is as follows: load the DR (which during an interrupt of AS RESTORE will contain the address of the cell which was going to be restored to the free list) into the link field of the PR designated by the tag register. This simple action will restore the PR stack to its initial depth before the call of the UNSTACK PR sequence. It should be noted that the value of the PR will have been changed when the contents of the cell which was going to be restored was loaded into it. There is no way to recover this value. Luckily there is no need to do so. After the interrupt has been processed, if the interrupt is a recoverable one, the TP control logic will continue with the instruction where it left off. This time the cell will definitely be restored to the available space list. Since the top of the PR stack is destined to be thrown away anyway it does not matter that the value field contains garbage. A pictorial example of UNSTACK is given in Figure h. 3- 2.1/3- 8A/69 Section U.3.2.1 - h/5 BEFORE AFTER PRN : 3 VALUE PR 14: 6 9 ,A p { ? 7> , 4 , s , 6 * 7 ■• 1 10 * — —j j K \ — > } K 10 i'i 1 prn: i VALUE PRI4: 3 9 1/2 1 I t 1 J v 3/4 5 6 7 8 1 r l 1 1 1 | v — v, — \ *=-^» — "■ — > FIGURE 4.3.2. 1/3 EFFECTS OF UNSTACK 5/19/69 Section U.3.2.1 - 5 PRSN SELECTOR WAS SET BY AS GET CALL: AS GET on return . LR :- DR YES PL2/E := 1 PR(lU) := LR m(xk) := LR MSTOR = 1 CELL SIZE=DW call: MEM. MODIFIED ENTRY on return YES y INTERRUFTXNO YES DR :*= SNR(TGR) MERGE DR -* LR INHIBIT BYTES 2, 3 DR := LR LR := PR(tGR) call: memory write PL2/E PR(TGR) T :=DR 1j ( return) I OSC = 1 if OS has been cleared OSINT = 1 if OS will need to be initialized Pointer Stack Sequences - Stack. PR Flow Chart Section if. 3. 2.1 P. 1/2 PL2/E:» 1 IBO/E:= 1 IBl/E:= 1 AB := PR(TGR) DR := PR(TGR) : OS CLEAR on return PL2/E := 1 DR := PR(TGR) YES YES DB := PR(lU) SET PRSN SELECT LOGIC CELL SIZE = W MSTOR := GO TO MEM. PRE-LNCREM. START PL2/E. ibo/e; IBl/'E DR := PR(TGi r /GO TO /INTERRUPT ' Ireturn IN A CALLING// ^ N SEQ.^> - 1 if OS has been cleared = 1 if OS will need to be initialized PL2/E := 1 PR(TGR) T := DR PROMOD := 1 YES YES CALL AS Rl'( Pointer Stack Sequences - Unstack PR Flow Chart 1+.3.2.2 STACK PR Control Logic The STACK PR sequence obtains a cell from available space and then loads it with the current contents of the Pointer Register link, value and segment name fields and places it in the pointer stack immediately "below" the Pointer Register. There are no control signals or flip-flops which must be set before entering this sequence. However, the sequence does make use of the CONS flip-flop, set by the AS GET sequence, if an interrupt occurs while executing the remainder of the sequence. Note that the STACK PR sequence changes the setting of the cell size selector logic. Thus when using this sequence due care must be taken if the selector was previously set. Another item to note is the operation of the PRSNR selector. Before the memory access, the selector is set to Segment Name Register #lk by the AS GET sequence. Once the core address has been calculated and the "load registers" signal, LDREG, turned on, this setting is no longer needed. At this point the PRSNR selector is switched to the Segment Name Register corresponding to the PR being stacked, and that segment name can then be stored in the stack in core. Interrupts during the sequence are handled in one of two ways. If the interrupt occurs during the AS GET sequence, a direct return can be made since the AS GET sequence insures that there are no "loose ends". Otherwise the operations described in Section U.3.2.1 must be performed before an interrupt return is made. 8A/69 Section U.3.2.2 - l/l PST10 DBPFi/G = 1 LRP/G = 1 NPRlU/S = 1 PLC2 = 1 WRPRV/E = 1 " PST11 DBPP/G = 1 LRP/G = 1 NPRlU/S = 1 WRPRL/E = 1 PST1 RASTR/S = 1 CALL AS GET PST2 YE£ YES DLR/G = 1 SCSC/S = 1 SMSR/S = 1 PST3 CCSD/E = 1 CALL '-MEM. MODIFIED ENTRY YES /INTERRUPT DBPR/G = 1 DRP/G = 1 PLC2 = 1 TNB/G = 1 WRPRL/E = 1 (return j Pointer Stack Sequences -STACK PR Control Step Flow Chart PSTl* BDR/G - 1 PRP/G = 1 PSNPRB/G ■ 1 SNRD/E ■ 1 SNS/G = 1 TNB/G * 1 t PST5 DLR/G DLR2/N = 1 DLR3/N = 1 PST6 LDR/G = 1 PST7 BLR/G = 1 PRP/G = 1 TNB/G = 1 " PST8 CALL: MEMORY WRITE 4.3-2.3 UNSTACK PR Control Logic The UNSTACK PR sequence is used in adjusting the PR stacks. During its execution the contents of the cell which was originally the second cell in the stack is stored in the PR at the top of the stack. Then this second cell is removed from the stack and returned to available space. The control logic itself is reasonably straightforward. The Boolean equations for the decision logic after control point PST13 are given in Figure 4.3.2.3. Note that the direct control lines to the cell size generator are used to specify the cell size for the memory access. This means that the contents of the cell size flip-flops remain unchanged. However, the cell size selector is changed and thus if the calling sequence desires some other selection, it must reset the selector after the UNSTACK PR sequence has returned. 8/4/69 Section 4.3-2.3 - 1/2 PSA013 • EQ PSTlU PSA013 • EQ • N13S • OSC PST15 PSA013 • EQ • (N13S OSC) v PSA016 PST1T Figure U.3.2.3 - Boolean Equations for Decision Logic After PST13 12/18/69 Section U.3.2.3 - 2/2 PST12 PST13 PST16 BDR/G = 1 PLC2 = 1 PRP/G = 1 TNB/G =1 PST20 GO TO AS RESTORE BAR/G = 1 BDR/G = 1 IBCO = 1 IBC1 = 1 PLC2 = 1 PRP/G = 1 REQ/E = 1 TNB/G = 1 CCSH/E = 1 SCSC/S = 1 TZ/E = 1 YES PST15 CALL OS CLEAR YES PST19 PST18 BDR/G =1 PLC2 =1 PRP/G =1 TNB/G =1 CCSW/E = 1 CALL MEMORY MODIFIED ENTRY V PST17 NPRlU/S = 1 RMSR/S = 1 SNS/G = 1 PST 21 DBPR/G = 1 DRP/G = 1 PLC2 = 1 TNB/G = 1 WRPRL/E= 1 PST22 PSTll* SSUF/S = 1 Pointer Stack Sequence - UNSTACK PR Control Step Flowchart h. h Phrase Processing This section describes the various phrase processing sequences called by the Main Control sequence and its component parts: the Primi- tive of the imprimitive sequences. The first section describes the Phrase Process Sequence, which, sets up a phrase in the IR and then calls the Pre-Operation sequence to process it. The Pre-Operation sequence, described in the second section performs the various pre-operations which may be specified by an Operand Phrase: pushing of the PR, modifying of the PR value field, etc. The remaining sections describe the Post-Operation Sequence, Increment ICT, which increments the instruction counter, IBR Reload and ' Exchange PR-SBR. 8A/69 Section k.h - l/l U.4.1 Phrase Process Sequence U.U.1.1 Phrase Process Sequence Description The Phrase Process Sequence is used to control the initial processing of a phrase. This includes checking the ICT for zero and reloading the IBR if necessary, loading the IR from the IBR, loading the tag register, TGR , from the leftmost byte of the IR and finally per- forming the phrase operations and ICT incrementation. In this sequence the phrase operation will not exchange PR#0 and the SBR if the TGR = 0. There is one option which is used in the imprimitive sequence which skips the phase operations and the ICT incrementation. 8A/69 Section U.4.1.1 - l/l MERG := MNEM := CALL : IBR Reload CALL: Phrase Seq. YES LNCPH := 1 CALL: INCR ICT YES MERG = MNEM = CALL - 1 IBR Reload 1 on return 1 NO YES [Interrupti U Return/) Phrase Processing Sequence Flow Chart Section l+.i+.l.l. U.H.1.2 PHRASE PROCESS Control Logic As shown in the control step flow chart at the end of this section, the Phrase Process Control logic is very straight forward. There is one control signal, SICT, which, if on, causes the sequence to skip around the phrase operations and the incrementation of the ICT. 6/11/71 Section lf.U.1.2 -1/1 w MUT8 NULL MUT9 YES MERG = MNEM = CALL : IBR Reload YES w MUT10 BIR/G = 1 IBR/S = 1 YES MUTL1 MERG = 1 MNEM = CALL: IBR Reload MUT12 CALL: Phrase Seq. YES DJCPH = 1 CALL: INCR ICT 1 ' MUT13 Phrase Processing Sequence - Control Step Flow Chart Section k.k.1.2 k.k.2 Phrase-Operation Sequence U.H.2.1 Phrase-Operation Sequence Description The Pre-Operation Sequence is used to perform the various PR operations which may be specified by the operand phrases before the instruction is executed. There are two entry points: the Phrase Sequence entry point is used by the operand phrases of the Primitiye and Imprimitive instructions, and the Operator Sequence entry point is used by the first operand phrase of the Imprimitive instructions. The Operator Sequence entry point does not check for the immediate option or the pre- slash since these are not allowed in the initial operand (operator) of imprimitive instruction phrases. The sequence is set up in such a manner that it assumes the phrase to be processed is always left- justified in the IR. The first operation of the sequence is then to load the tag field from the left- most byte of the IR into the TGR. Next if the tag register is 13 the OS must be cleared. This insures that if the operand stack is accessed by means of a PR reference all data in the hardware registers of the TP will have previously been put into core memory. If the sequence was entered by way of the Operator Sequence entry point and if the phrase is short and not indirect the sequence is finished. If the sequence was entered by the Phrase Sequence entry point then the IMM flip-flop must be set provided that the instruction can have the immediate option and that the IR8 bit is 1. If no push of the PR is indicated by the phrase and if the phrase is short and not indirect then the sequence is finished. If further operations are necessary then a check for TGR = is made provided that the CKTGZ signal for the Phrase Process sequence has been set to one. Next if the Phrase Sequence entry was used and if IR5 is 1, then the PR stack sequence must be executed. If an interrupt occurs 6/11/71 Section 1+.1+.2.1 - 1/1+ in this sequence the STACK PR control logic will assure that the TP returns to its state prior to the call. Then in order for the PRE-OP sequence to return the TP to its state before the PRE-OP sequence was called, all that is necessary is to reexchange the PR and SBR if this had been done previously. Then an interrupt return can be performed. If there was no interrupt and if the phrase is short and not indirect, then the sequence is finished. Otherwise it continues with both entry points using the same operations for the rest of the sequence. Next, if the phrase is short, a single indirect address is per- formed and control of the sequence is given to the final check of the tag, register for a tag of zero. If the phrase is long and the indirect modifier option is being used, the tag register must be loaded with the secondary tag, i.e. the tag field from the second byte in the IR (bits 10 through 13). If the secondary tag is 15, the AR is then loaded from the OS, otherwise the AR :j is loaded with the value field of the designated PR. When no indirect modifier option is specified, the AR is loaded from the modifier field in the IR. At this point the AR has been loaded, right -justified, "with a two -byte modifier field. The next step is to determine what to do with this modifier. If the modification option is addition the modifier is added to the PR value designated by the primary tag. If replacement is specified the modifier replaces the value. 6/19/69 Section U.U.2.1 - 2/ If conditional subtraction is indicated the modifier is sub- tracted from the PR value and the appropriate actions are taken depending on the result . Finally if the PR has been modified during the sequence, the tag is checked. If the tag is zero, PROM0D must be set to one. It should be noted that all interrupts which may occur as a result of this sequence can be "bucked upstairs", provided that certain assumptions can be met. In the logic, if an interrupt occurs after the PRE-OP sequence has stacked a PR, then in order to restore the TP to its original state the PR must be unstacked before the sequence can make an interrupt return. However in the most general case an interrupt could occur in the UNSTACK PR sequence ; thus this operation could not ordinarily be performed after one interrupt has occured since there is no provision for the control logic to handle stacked interrupts, To circumvent this difficulty and to execute the sequence we have assumed that it will not be interrupted if the preceding STACK PR sequence was OK. This reasoning is based on the fact that UNSTACK PR cannot cause any interrupts except those concerning the accessing of the cell being unstacked and this is identical to the cell which was previously manipulated by STACK PR. Thus no interrupt will occur in the UNSTACK PR sequence if the following conditions are met: 1) The previous STACK PR sequence call did not generate an interrupt . 2) A cell which can be written into without being interrupted can be read without being interrupted. 3) No change of a System Name Table is possible while the program using it is active (i.e. running on a TP). h) No hardware failure occurs in the memory box containing the unstacked cell between the time the STACK PR and UNSTACK PR sequences are executed ( several hundred nano-seconds ) . 6/19/69 Section k.U.2.1 - 3A Given the Operating System constraint detailed above, only this last occurrence is actually possible. However, its probability of occurrence should be exceedingly low. Therefore we shall go ahead and perform the UNSTACK PR sequence if necessary during an interrupt. If an interrupt does occur due to violation of assumption U, two dif- ferent interrupt conditions will be set when the Interrupt Control sequence is executed. This can be treated as a fatal interrupt for the program since a hardware memory error usually is just that. 8A/69 Section U.U.2.1 - k/k (RETURN j] YES NO SBRSW := 1 CALL: EXCHANGE PR-SBR YES YES on return NO YES CALL : OS CLEAR YES YES IMM := 1 CKTGZ YES on return SBRSW := CALL: EXCHANGE PR-SBR ENTRY CALL: UNSTACK PR Phrase Operation Sequence Flow Chart Section 4.1+.2.1 P. 1/2 / Entry \ TGR:- IR(0) YES YES Cell size=H MSTOR =0 CALL : MEMORY DIRECT ACCESS on return PL2/E =1 PR (TGR) :=LR PL3/E IBO/E IB1/E AR DR := 1 := 1 := 1 := IR := IR YES YES conditional subtraction CSA := 1 DR LR DR := AR := -DR := LR DB:= PR(tGR) AR: = DR+DB Cell alze=H POP :=1 CS2C :=0 CALL: OS EHTRY DB:- PR (TGR) PL2/E: IBO/E:= 1 IBl/E:= 1 AR :- DB DR := DB TGR :- IR(O) DB:= PR (TGR) AR:= DR+DB PR(TCR) :««AR YES OPANDF PROMOD := SBRSW = 1 CALL: EXCHANGE .PR-SBR Phase Operation Sequence Flow Chart NEC STOR NWTOS CALL: OS READ = = 1 = J ENTRY ] Section 1+.U.2.1 P. 2/2 U.U.2.2 Phrase Operation Control Logic The PHRASE OPERATION sequence performs all of the necessary pre-operations on an instruction phrase. The control logic involved is pretty extensive. MU3T is rather complicated since it can "be entered from three different positions and each position causes a slightly different set of gates to be turned on. Note that IBCO, IBC1, BAR/G, and REQ/S are always turned on. The other signals are chosen as shown in Figure k. h. 2. 2/1. Note that MU3T will have to remain on long enough for the longest operation to take place. In order to negate the quantity in the AR for a conditional subtraction, control points MUUO and MUUl gate the AR into the DR } generate all l's on the DB and perform an exclusive or into the LR. A carry is then injected in the low order bit during the addition in order to make the final result 2's complement. Note that MUU5 performs one of two functions depending on which control point activates it. Note that MU3T leads directly to MU38. This is not strictly necessary when IR7 = since in this case the TGR was not loaded from the second byte in the IR (byte No. l) and there is thus no need to reload it from the leftmost byte again (byte No. 0). However since MU38 will take relatively little time the logic necessary to skip around it seemed to be a waste. 6/11/71 Section U.U.2.2 - 1/2 < 1 > IF >n "7 m ...S **s CD ( * ( \d 1 ^__> : _j — x N 1 s^ . . , JO a ISO *4 J° \ — x N 1 S9 r )o [Jo k A' *— I ' MU37 IBCO BAR/G REQ/S PL3C IRP/G BDR/G TNB/G PRP/G PLC2 Figure U. 4.2.2/ 1 Task Signal Logic for MU3?~ 6/11/71 Section 4.4.2.2 - 2/2 [[RETURN )] t MlJT27 b MUT28 IRTGO/G = 1 YES YES CALL: OS CLEAR YES X)PSQSTRT=1 on return PHSQIR2 YES IMMINS=L \ YES MUT29 SIMM/S = 1 YES PHSQG1 MUT30 SBRSW = 1 CALL: EXCHANGE PR-SBR on return MUT31 CALL: STACK PR on retur YES PHSQG3 MUI031 YES Phrase Operation Sequence - Control Step Flow Chart Section k.h.2.2 CCSH/E = 1 RMSR/S = 1 SCSC/S = 1 CALL: MEMORY DIR. ENTRY DBFR/G = 1 LRP/G = 1 PLC2 = 1 TNB/G = 1 WPRV/E = 1 NWTOS = 1 SSTOR/S = 1 CALL: OS READ Fhrase Operation Sequence - Control Step Flow Chart i MIJT37X Section U.lt.2.2 WSlkh on return SBRSW = 1 CAT EXCHANGE PR-SBR Phrase Operation Sequence - Control Step Flow Chart Section k.k.2.2 P. 3/3 i k . h . 3 Post-Operation Sequence U.U.3.1 Post-Operation Sequence Description The Post-Operation Sequence is used to perform the post- slash operations as called by the Final Control sequence. There are in effect 3 separate entry points which perform the same operations but test different bytes in the IR. The Post-Op sequence performs its operations using the phrase data stored in the Oth byte of the IR. The Post-Op 1 and Post-Op 2 sequences use the 1 and 2 numbered bytes in the IR. The operations consist of loading the TGR with the proper bits from the IR, and then testing the post-slash bits. If there is no post-slash the sequence returns. If there is a post-slash the sequence calls the Unstack PR sequence after which it tests for a TGR of 0. If the TGR = and there are both pre-and-post-slashes , PR0M0D is set to zero. Then the sequence returns. 3/15/71 Section U.U.3.1 - 1/ YES TGR: = IR(O) CALL: UNSTACK PR ENTRY YES 'Go To\\ /INTERRUPT \ IRETURN IN YES PRCMOD := :: *- [RETURN J! YES TGR:= IR(l) call: unstack pr ENTRY YES YES PRCMOD := NO " ^ YES IR(2) TGR CALL : UNSTACK PR ENTRY YES PRCMOD := NO " (f RETURN ] ] Post - Operation Sequence Section U.U.3.1 P. 1/1 U.U.3.2 POST-OP Control Logic The three versions of the POST-OP sequence are all implemente using the same control points. Note that since the POST-OP sequence ma be called 3 times in a row in the Final Control Sequence, care must be taken when designing the logic so that the sequence will have time to reset itself before being called again. 8/19/71 Section U.U.3.2 - 1/1 MUT25 YES IRTGO/G = 1 MUT26 CALL". UNSTACK PR on return YES MOT25 MUT26 YES IRTGl/G = 1 call: UNSTACK PR on return YES MQT25 IRTG2/G = 1 MUT26 call: unstack pr on return MUT27a RPRCM/IS » 1 Post - Operation Sequence - Control Step Flow Chart Section 4.U.3.2 P. l/l k.k.k Increment ICT Sequence k. k.k.l Increment ICT Sequence Description The INCR ICT sequence is used to increment the ICT by +1 or +2 and then to check for overflow. If there is an overflow, PR#0 must he incremented by 8. Another option is available in which the ICT will be incremented past the current operand phrase whose contents are being held left-justified in the IR. In this situation the ICT will be incremented by 1 if the phrase is short and 3 if the phrase is long. 8/U/69 Section k.k.k.l - l/l / INCR \ ( ICT I \ NO ITWO= 1 YES ICT:= ICT+2 ICT:- ICT+1 YES INCPH = 1 - increment ICT over phrase ITWO = 1 - increment ICT by 2 Increment ICT Sequence Flow Chart Section k.k.k.l P. l/l U.U.U.2 INCR ICT Control Logic The INCR ICT sequence is entered via a null control point so as to allow the initiating signals to change state without adversely- affecting the sequence. Next, the signal ITWO is used to determine whether there are two operands or not. If two, ICT2/E is turned on, incrementing the ICT by 2 bytes. If not, ICTl/E is turned on, incre- menting the ICT by 1 byte. Then the signal INCPH and IR9 are directed to determine whether the ICT should be incremented past the phrase ( INCPH = l), and whether the phrase is long or short (IR9). For a long phrase, the ICT is incremented by 2, resulting in a total increment of 3 bytes. The signal ICTOV indicates an ICT overflow. If an overflow has occured, control points MUT17-19 are used to increment PR#0 by 8. 8/24/71 Section k.k.k.2 - 1/1 MOT15 ADD/K- 1 ADD2/N- 1 ADD3/N- 1 P8/E- 1 m MUT19 ARP/ttp 1 DBJR/O- 1 WRFKL/E- 1 WRJKV/E- 1 Increment ICT Control Step Flow Chart Section k.k.k.2 P. 1/1 k.k.5 IBR Reload Sequence The IBR Reload Sequence is used to reload the IBR whenever it is emptied and the complete instruction has still not been obtained, It is used by all of the Main Control Subsequences: Primitive and Imprimitive. Q/k/69 Section U-U. 5 - l/l ^.4.5.1 I BR Reload Sequence Description The IBR Reload Sequence consists of two parts: loading the Instruction Buffer Register with the next double word in the instruction stream and merging the new data into the IR. The first half is accomplished by adding 8 to the contents of PR#0 and making a double-word read access to memory. The second part requires quite a bit more explanation. As was mentioned in Section 2.6.1.2, if the ICT is greater than h at the beginning of an instruction fetch, a "wrap-around" will occur when the IR is loaded from the IBR. Thus one or more of the initial bytes of the IBR will be loaded into the IR following the valid instruction bytes. If, subsequently to this, the IBR is reloaded, it will be necessary to reload these "invalid" instruction bytes in the IR with the correct ones which were just stored in the IBR. However we must not destroy the valid instruction bytes in the IR since these particular bytes are no longer in the IBR. The way to do this involves a merging circuit connected to the control logic of the Permuter. There are several considerations. First, if there is a mnemonic byte in the IR (this will be true in all imprimitive and non-PAU primitive instructions and also in the first access for PAU instructions), the first byte of good data will be in the rightmost byte position. Second of all, the logic must set the gate inhibit signals of the IR. The permutations are easily taken care of by the Permutation Control Logic (See Mainframe Logic Book Drawing 0^-7). If a mnemonic byte is present OPJ/E is turned on. Thus the merge logic need only take care of the inhibiting signals as shown in Figure k.k. 5.1/1. 12/23/70 Section U.H.5.1 - 1/5 For non-mnemonic byte reloadings if ICT = Gate Inhibits 111 0, 110 0, 1, 10 1 0, 1, 2, For mnemonic byte reloadings if ICT = Gate Inhibits 111 3, 110 3, 0, 10 1 3, 0, 1, Figure k.k. 5.1/1 - Signals Used In IR Merging 12/18/69 Section U.U.5-1 - 2/5 The logic necessary for the merge circuit control is shown in Figure U.H. 5.1/2. Note that there are two merge signals. The one which is used depends on the type of merge. The logic equations for this circuit are as follows : BIRO/N = MGIM v.MGPM •(ICT2 v ICT3) BIR1/N = MGIM«(lCT2 v ICT3) v MGPM • ICT2-ICT3 BIR2/N = MGIM*ICT2 • ICT3 BIR3/N = MGPM These equations are implemented using a -236 diode matrix board or the IC chip logic shown in Figure H.H.5.1A. A flowchart showing the operations necessary to reload the IBR and merge it into the IR is given at the end of this section. 12/22/70 Section U.^.5.1 - 3/5 MGM/E MGS/E ICT3 ICT2 ICT3 r> o B)/ O- Rl" Si! Figure U.U.5.1/2 IR Merge Control Logic 10/22/69 Section U.U.5.1 - *+/-5 BIR3/N uses 3 IC chips time: 1 collector delay after gate signal Figure U.U.5.1/-3 IC Realization of IR Merge Control Logic 10/22/69 Section U.U.5.1 - 5/5 DR: « PR(O) Set Seg.NameSel. DB: ■ +8 AR: « DR + DB DR:>AR MSTOR: - CELL SIZE -D GO TO MEMORY PRE- IRC. START MEMORY \YK INTERRUPT IBR1 := LR IBR2 := DR NO [return ] HEgQ l 1 -> "» ^ «air J°- MERGE ibr(ictK ir OPJ/E := IBR Reload Sequence Section U.l*.5-I P. l/l k.k.5.2 IBR RELOAD Control Logic The IBR RELOAD ENTRY control logic makes use of two control signals: MERG which is a 1 if after the IBR is loaded a merge into the IR is desired, and MNEM which is a 1 if the IR contains a mnemonic byte and must therefore be loaded into the IR as shown in Figure k.k.5,2. IR PHRASE DATA ■ i MNEMONIC Figure k.k.5.2 IR Format for Mnemonic Bytes There are no significant complications in the control point logic. However it should be noted that in performing the memory access the cell size selector is switched to the control select option for double words. This means that the original setting is lost. In most cases this in unimportant since the IBR RELOAD sequence is usually executed before the cell size option for the instruction has been selected. 8/19/71 Section U.U.5.2 - 1/1 MU1 MU2 MU3 BDR/G = 1 PRP/G = 1 SNS/E = 1 NO YES YES MGS/E = 1 ADD/E = 1 ADDO/N = 1 ADDl/N * 1 P8/E = 1 ARP/G = 1 BDR/G = 1 RMSR/S = 1 SCSC/S = 1 MUH CCSD/E CALL: MEM. PRE-INC START ON RETURN DRP/G = 1 IBR/S = 1 IBRC/S = 1 IBRC^/E = 1 WRIB/E = 1 MGM/E = 1 OPJ/E = 1 MUTx MUT BIR/G = 1 IBR/S = 1 (return J IBR/S = 1 IBRC/S = 1 LRP/G = 1 WRIB/E = 1 TP Main Utility Sequences IBR Reload Control Step Flow Chart h.k.6 Exchange PR-SBR Sequence k.k.6.1 Exchange PR-SBR Sequence Description The Exchange PR-SBR Sequence allows for an exchange of value fields between two registers of the TP (usually a PR and the SBR). This sequence is used fairly often in the imprimitive sequence since the SBR is used as a temporary storage register for various PR values. In general the sequence loads the DR with a pointer register and the LR with the SBR. The PR can either be PR#0 or be determined by the TGR. After the DR and LR are loaded from their chosen storage registers, the LR is stored into either the PR indicated by the TGR or PR#0. Then the link portion of the DR is loaded into the same register. This in effect results in only an exchange of value fields and flags while the link field remains unchanged. If it is desired to also load the SBR, then the DR is stored in the SBR. There is no need to worry about the link field of the SBR since it does not contain anything valuable during an imprimitive instruction. There is one other option allowed in this sequence. If desired, bit 9 of the LR can be set according to the state of the EXEC flip flop before the LR is loaded into the PR. This in effect will set the execute flip flop of the pointer register. The flowchart for this sequence follows at the end of this section. 6/13/69 Section k.k.6.1 - l/l Ifi := SBR DR := PR(NB) LR9 == YES LR9 == 1 PR(NB) :- IM FLPR/N :=. 1 ER(NB) L := DR SBRSW = 1 N YES SBR := DR f return) Exchange PR-SBR Sequence Flow Chart Section k.k.6 k.h.6.2 Exchange PR-SBR Control Logic The Exchange PR-SBR Control logic uses four control signals which are set if necessary "by the calling control point. NBTAG is set to 1 if the pointer register being switched is to be designated by the tag register. Otherwise PR#0 is used. SETEX is set to 1 if the execute flag of the PR in the exchange of data is to be set according to whether or not the EXEC flip flop is on, i.e. whether or not an EXECUTE instruction is being performed. If SETEX is 0, the value of the execute flag will be exchanged like all the other data. SBRSW is set to 1 if it is necessary to load the data from the PR into the SBR. In some cases at the end of the imprimitive sequence there is no need to reload the SBR since the data will never be used. In these cases SBRSW is left off. In control point MNT32 it should be noted that the RLR9/S and SLR9/S signals will force LR9 and LR9 respectively to zero, which in turn will cause the LR9 bit to stay in the desired state. 6/13/69 Section k.k.6.2 - l/l ' r MUT20 MUT20x 3DR/G = 1 PRP/G = 1 TNB/G = 1 " MUT21 BLR/G = 1 PRP/G = 1 SBR/S = 1 YES EXEC 2 l^™ 3 RLR9/S = 1 MJT23 THB/G = 1 DBPR, LRP, "R/G = 1 '/G = 1 WRPRL/E= 1 WRPRV/E= 1 MUT2I+ TNB/G - 1 DBPR. DRP, SBRSW = 1 \YES_ MOT22X SLR9/S = 1 DBPR/G = 1 DRP/G = 1 SBR/S = 1 WSBL/E - 1 WSBV/E = 1 Exchange PR-SBR Sequence - Control Step Flow Chart Section k.k.6.S P. l/l k.5 Operand Stack Operations The Operand Stack Operations are those processes which are common to all instructions and sequences which use the Operand Stack. These operations are broken down into two groups: the basic OS sequen- ces which perform the operations directly needed to read from and write into the Operand Stack, and the supplementary OS sequences which per- form clearing and initialization operations. 8/19/71 Section U.5 - 1/1 k.5.1 Basic OS Sequences 4.5.1.1 Basic OS Sequence Descriptions The Operand Stack is controlled through the use of several basic OS sequences: the OS ENTRY sequence, the SCR MOD sequence, the OS READ sequence and the OS WRITE sequence. These sequences directly control the manipulation of the OS hardware and are used by all control sequences which must access the OS. The flowcharts describing these sequences are given at the end of this section. The purpose of the OS ENTRY sequence is to check for potential overflow or underflow in the Operand Stack. The sequence makes sure that the portion of the Operand Stack which will be utilized in the execution of the instruction is available in the 0S fast registers in the TP. If overflow or underflow is going to occur, the sequence makes the proper number of memory accesses to unload or fill the Operand Stack so that sufficient storage space is available for the operands. To deter-' mine how many bytes are needed in the stack, this sequence must know the j type of operation (push or pop), the cell size (byte, halfword, word or double word) and the number of cells used (one or two). The sequence begins by checking the type of instruction. If the instruction is a "pop" type a check must be made for underflow; alternatively if it is a "push" type an overflow check is made. In certain cases, i.e. , the DUP instruction, it may be necessary to both read from the present stack and write additional data into the stack. This necessitates both an underflow and an overflow check. The checks themselves involve using the overflow/underflow logic described in Section 2.3-1.4. The signals generated by this logic are valid as soon as the logic settles down after a change in the OSTR or SCR, i.e., the logic does not have to be "turned on". If an 7/31/69 Section 4.5.1.1 - l/6 overflow or underflow condition is detected it is corrected by making a memory access using the OSTR and either loading or unloading the proper 0S fast registers. There is one slight problem in using the OSTR. In order to get the full l6-bit virtual address of the double word in core which must be accessed, the OSTR must be masked into the low order 5 bits of the value of PR#13 (the lowest 3 bits are set to 0). However if the SCR has wrapped around the 31-0 byte boundary in the OS fast register storage, PR#13 will have been incremented by 32 and the wrong address will be obtained (see Figure U.5.1.1). To correct this, the flip-flop WRAP is set to 1 every time the SCR and OSTR are pointing to different sides of the 31-0 byte boundary. The state of WRAP can be controlled by adjusting it each time either the SCR or the OSTR crosses the boundary. Thus when the OSTR is used in constructing an address, if WRAP = 1, then 32 is subtracted from the address before it is sent to the Memory Access Sequence. As will be seen later the overflow correction part of this sequence is also used by the OS CLEAR Sequence. When this happens a special test is made before the OSTR is incremented. If the OSTR and the high order bits of the SCR are equal (and the OS not full) a special return is made to the OS CLEAR sequence without incrementing the OSTR. After the check has been made (and corrected if necessary) control returns to the calling sequence. The SCR MOD Sequence is used to increment (SUB = 0) or decre- ment (SUB = l) the SCR. This is done using the constant generator which generates a value equal to one or two times the cell size (depending on the number of cells which are needed). If the instruction is a "push" type this value is positive; if it is a "pop" the value is negative. 7/31/69 Section h. 5.1.1 - 2/6 31-0 OVERFLOW BOUNDARY 00 01 OSTR=- -0|llOOO SCR = i loom •6 th BIT FROM (PRI3- 32) .th 6 ,n BIT FROM (PRI3) Figure k. 5.1.1 - SCR Overflow and Its Effect on the OSTR and PR#13 If the SCR and the OSTR points to different sides of the 31-0 boundary, their virtual addresses will differ by 32. However, high order bits (from the 6th least significant bit on up) are not returned by the SCR and the OSTR registers. By definition PR#13 reflects the value of the SCR. Accordingly whenever the address of the OSTR is desired, PR#13 will have to be adjusted by -32. 7/31/69 Section U.5.1.1 - 3/6 This value is then f dded to the current value of the SCR, using the 5-bit Adder. If there is an overflow on addition, or underflow upon subtraction, the A50V flip-flop will he turned on — indicating that the SCR has passed the 31-0 byte boundary in the OS. Then if the change is to be permanent and if it is alright to destroy the contents of the AR, DR and LR the value of PR#l3 is changed by +32. When this happens WRAP is set /reset according to the "direction in which the SCR is moving". If PR#13 must not be incremented/decremented at this time, the DECPR flip-flop is set to indicate that it should be adjusted as soon as it is safe to do so. Then the control returns to the calling sequence. Note that the SCR MOD sequence is also responsible for determining the state of the OS full flip-flop, OSF. As described in section 2.3.1.^, this flip-flop is used to determine whether the hardware registers are full or empty whenever the new SCR position equals the OSTR position. In order to perform this operation, the SCR MOD sequence resets OSF immediately before incrementing the SCR. Then before the SCR is permanently changed, the OSF setting logic is activated to check for the necessary conditions for OSF to be on and to set OSF if necessary. The OS WRITE sequence takes a data cell stored left-justified in the LR (and DR if the cell is a double-word) and writes it into the Operand Stack. It also increments the SCR by the cell size so that it will again point to the start of the first unfilled cell. The OS READ sequence first uses the SCR MOD sequence to position the SCR so it points to^the beginning of the desired cell. This means that the SCR must be decremented by one cell size if the top operand is being read (CS2 = l). If the read is a "store" type, i.e., the final SCR position is the same as the initial, or alternatively if the WAIT signal is on, the SCR MOD sequence is not allowed to change PR#13 even if there is a wraparound. After the SCR value has been decremented, the new value is used to read out the desired cell, (i.e., the modified SCR value is fed to the byte selection circuit). If the data is to be returned in negative 8/25/69 Section k. 5.1.1 - k/6 form (i.e. NEG = l), the "gate false out" control is used for the OS. Otherwise the "gate true out" is used (see Section 2.3.^). If the NWTOS signal is on, the output is placed on the DB only. Otherwise it is also loaded left-justified into the LR (and DR if the cell is a double word). Note that a double word number will never be requested in l's complement form. Finally, if the access to the OS is of a "store" type, the SCR is incremented back to its original position. Note that in this case manipulation of PR#13 is again inhibited. One persistent problem which occurs in using the OS is the problem of detecting the "top" and/or "bottom" of the storage area allocated to the OS. There are no built-in safeguards within the OS. There are no built-in safeguards within the OS logic itself since any procedure which was truly effective in the general case would involve a prohibitive amount of logic. In order to provide a minimum amount of hardware protection several conventions have been specified. First of all, Operand Stack storage areas should always be allocated their own separate segments. This will keep the TP from accidentally spilling out of the stack area, into an area where it does not belong. If an access beyond the confines of the OS storage segment is attempted, a bounds overflow interrupt will result. Even with this type of protection, there is another way that one might get into trouble. This problem is a result of the wraparound effect when pointer registers are incremented above 2 or decremented below 0. If an operand stack segment has been allocated 256 pages of core, the wraparound at either end of the OS segment will not cause a bounds overflow interrupt since both extreme addresses are within the segment. This wraparound would, in general, be a very undesirable effect and yet might very easily happen if due to some error the program loses track of how much data it has in the OS. . 8/25/69 Section k. 5. 1.1 - 5/6 The solution to this problem involves checking the 32-bit adder overflow signal everytime PR#13 is incremented or decremented due to an SCR wraparound at the 0-32 boundary. If an overflow in the 32 -bit adder occurs during this calculation, a PR#13 wraparound has occurred and the OS segment boundary has probably been fouled up. The above check is made in the SCR MOD sequence if the value of PR#13 is changed during its operation or whenever the calculation is performed if it does not occur during SCR MOD. It must also be made when OS entry uses PR#13 + 32 to access core. These checks will catch any wraparound attempt by the TP hardware during the execution of instructions involving the OS. However, it probably will not catch a wraparound caused by independent manipulation of PR#13 by the programmer 8/25/69 Section U. 5.1.1 - 6/6 I ENTRY J OSTR := OSTR-8 A50V := OVERFLOW CELL SIZE := DW MSTOR := DR := PR(13) OSTP/G = 1 SET PRSN SELECTS YES WRAP := 1 DB AR DR -32 DB + DR AR CALL: MEMORY (MODIFIED ENTRY) OSTR := OSTR+8 A50V = OVERFLOW YES OSBER := i /A50V YES NO l 1 WRAP := ' 1 / *i TR2 := OSTR 0S(TR2) := LR TR2 := 0STR+1( 0S(TR2) := DR CELL SIZE := OLD VALUE Operand Stack - Basic Operations OS ENTRY Sequence Flow Chart Section I4-.5.I.I P. 1/k f PUSH \ f CHECK L. CELL SIZE :« DW MSTOR : = 1 DR := PR(13) OSTP/G :- 1 SET PRSN SELECTS NO DB AH DR 32 DR + DB AR CALL: MEMORY (MODIFIED ENTRY) ON RETURN YES YES / INTERRUPT\NO T YES/ INTERRUPT T 10 OSTR :» OSTR+8 A50 V :- OVERFLOW CELL SIZE ■ OLD VALUS Operand Stack - Basic Operations OS ENTRY Sequence Flow Chart OSBER := 1 TR2 := 0STR LR := OS(TR2) TR2 := OSTR+1* DR := OS(TR2) CALL: MEMORY WRITE ACCESS WRAP Section 4.5.1.1 P. 2/h NO YES K = -CS -CS*CS2 HO K: +CS +CS*CS2 TRI = SCR+K OSF: = A50V = OVERFLOW SET OSF IF NECESSARY SCR: = TRI YES DR: = PR(13) DB: = -32 WRAP: = YES YES DECPR: AR: = DR+DB DR: - PR(13) DB: * +32 WRAP: - 1 OSBER: FLPR/N: = 1 PR y (l3): = AR Operand Stack - Basic Operations SCR MOD Sequence Flew Chart Section h. 5.1.1 P. 3 A ? \YES STOR =1 S/E := 1 DECPR := CS2C := CALL: SCR MOD DB := -0S(TR2) DR := DB YES YES S/E = CS2C = WAIT = 1 CALL SCR MOD DB := +0S(TR2) DB := DB W IT := 1 TR2 := SCR TR2 := SCR+lt YES YES DB := -0S(TR2) DB := +OS(TR2) LR := DB HO YES (7\ \ WRITE J~ TR2 := SCR 0S(TR2) := LR CSD « 1 MO CS2C := S/E :•= CALL: SCR MOD ( RETURN j YES TE2 :« SCR+U 0S(TR2) :■ DR Operand Stack - Basic Operation Sequences OS READ and OS WRITE Sequence Flow Charts Section 4.5.1.1 P. h/k k. 5.1.2 OS ENTRY Control Logic The OS ENTRY control logic is governed through the use of one control flip-flop, POP, and one control signal, CS2C, both of which are set before entering the sequence. POP equals 1 if the OS sequence is one in which data must be read from the stack and if data must be written into the stack. CS2C is 1 if 2 cells rather than one will be written into or read out of the stack. The first part of the sequence consists of checking the control signals together with the overflow-underflow indicators to see if anything must be done (refer to Figure k.5.1.2) . The gate signals 0SG1 through 0SG6 are indicated on the flowchart at the end of the section. The decision logic involved is implemented in standard integrated circuits. The decision logic eventually generates either a return signal, in which case the sequence is done, or it activates 0ST1 which sets the OVLOOP /UNLOOP flip-flop to the type of operation to be performed (i.e. overflow correction, in which case data must be taken from the memory and stored in the hardware registers or underflow correction, in which case data must be taken from the hardware register and stored in memory). If either type of correction is necessary, cont: will then be transferred to 0ST2. The OVLOOP and UNLOOP signals are used to control the flow of the control sequence and the operations which are performed. Since it is impossible to have both an underflow and overflow condition arise on the same access to the OS ENTRY sequence, and since the operations involved in these two cases are quite similar, it is advantageous to use the same control points for both operations when- ever possible. In control points, 0ST2 and 0ST15 , the Operand Stack full flip-flop OSF is reset. There is never any need to set the OSF in the OS ENTRY sequence since during corrections for possible stack overflow or underflow the OSTR is always moved away from the SCR. 7/2/70 Section k. 5-1.2 - 1/k (OSENSTRT • POP) • CS2C • UV2 v (OSENSTRT • POP) • CS2C • UV1 v OSG1 underflow- segment (OSENSTRT • POP) • 0V2 • CS2C v (OSENSTRT . POP) • OV1 • CS2C v (OSENSTRT . POP) . (UV2 • CS2C ) • DUP • 0V2 v (OSENSTRT • POP) • (UV1 • CS2C) . DUP . OV1 v (OSGUvOSG6) v OVENSTRT overflow segment (OSENSTRT • POP) • (UV2 • CS2C) • DUP v (OSENSTRT. POP) . (UV1 ♦ CS2C ) • DUP v (OSENSTRT • POP) • (UV2 . CS2C) . DUP * 0V2 v (OSENSTRT • POP) • (UV1 ♦ CS2C) ♦ DUP . OV1 v (OSENSTRT • POP) • 0V2 ♦ CS2C v (OSENSTRT • POP) • OV1 * CS2C v (OSG2vOSG3vOSG5) return Figure U. 5.1.2 - OS ENTRY Input Decision Logic 8/1/69 Section U.5.1.2 - 2/1+ Note that in OSTU the AOV signal is checked and, if active, is used to set the Operand Stack Bounds Error flip-flop, OSBER. This is one of the checks for PR#13 wraparound which was discussed at the end of Section k. 2. 2.7.1. Another point to notice is that in OS underflow before contr< step 0ST9, it is not necessary to load the OSTR into TR2. This is because in the underflow case, TR2 was previously loaded with the same contents as the OSTR in control step 0ST3 and no operations have been performed on either in the meantime. Thus they have the identical con- tents. In control point 0ST16 the cell size selector is set to the CSS/E signal so that the Overflow-Underflow logic in the OS Control group can determine whether another cycle is necessary. It should be noted that at the beginning of the sequence the CS selector has already been set by the calling sequence. Then the selector is changed during the memory access so that the control logic can force a cell size of double word to be used. If only one cycle is performed, the sequence will perform an exit with the selector enabling CSS/E and it will be up to the calling sequence to reset the cell size selector if necessarj If a second cycle is necessary, it will be assumed that the cell size is determined by CSS/E . Since all the cases which do not ha 1 cell sizes determined by CSS/E also do not need two double word cells (which is the only case which might need a second cycle) this is a safV assumption. Control point 0ST19 is a dummy control point. It is used in order to provide proper switching in the decision logic which uses the OS overflow-underflow signals. Since these signals will be changing during the operation of control point 0ST16 (due to the change of stat- in the cell size signals caused by turning on SCSS/S) it is not possib: to have decision logic immediately following 0ST16 , which depends on these changing signals (see section U.A.2). Thus 0ST19 is used to pro vide an advance out signal which can be used to activate the OS over- flow-underflow checking logic. 7/2/70 Section k. 5-1.2 - 3A In the original design of this control logic the number of control points was diminished by combining 0ST1 and OSTl^, 0ST2 and 0ST15, 0ST8 and 0ST11, and 0ST9, 0ST10 and 0ST13. However, the added complexity of the resulting logic around these control points almost negated the savings in control point logic. In addition, the speed of the circuit was reduced and the circuit as a whole was much more diffi- cult to understand. For these reasons, the present version with addi- tional control points was selected. The other aspects of this control logic are fairly straight- forward. 8/18/71 Section k. 5.1.2 - k/k YES 0SG1 OSG2 DUMMY CP OST19 YES SUNLP/S = 1 OST1 NPR13/S = 1 PRP/G = 1 BDR/G = 1 SNS/G = 1 OSTP/G = 1 SCSC/S = 1 S/E = 1 CINJ = 1 OSCU/G = 1 RMSR/S = 1 OSCG/E = 1 X2 = 1 OTA/G = 1 KB/G = 1 ADD5/G = 1 OST2 T1ST/G = 1 T1R2/G = 1 ROSF = 1 0ST2x 0ST2y 0! YES M32/E = 1 ADD/E = 1 CINJ = 1 SWRP/S = 1 OS' ARP/G = 1 BDR/G = 1 OST5 RWRP/S = 1 YES OST18 YES SOSBE/S = 1 os:. 0ST7 CCSD/E = 1 CALL: MEMORY MODIFIED ENTRY RSE/S = 1 OSC8/E = 1 OSCG/E = 1 X2 = 1 OTA = 1 KB/G = 1 ADD5/E = 1 OST17 ON RETURN' YES ST2y / INTERRUPT^ NO DRP/G = 1 DBOS/G = 1 RSD/E = 1 DBRJ = 1 OST12 OST9x SCSS/S = 1 WAIT FOR OV/UV LOGIC OST16 T1R2/G = 1 S/E = 1 OSCtyE = 1 OSCG/E = 1 X2 = 1 OTA/G = 1 KB/G = 1 ADD5/E = 1 OST11 0ST2y LRP/G = 1 DBOS/G = 1 RSD/E = 1 DBRJ = 1 OST; OST OS ENTRY - Control Point Flow Chart / PUSH \ CHECK h ( RETURN J (RETURN ] YES SOVLP/S = 1 OST1 NPR13/S = 1 PRP/G = 1 BDR/G = 1 SHS/G = 1 OSTP/G ■ 1 SCSC/S = 1 SMSR/S = 1 0ST2 OST2w M32/E = 1 ADD/E = 1 CINJ = 1 SWRP/S = 1 OSTl* SOSBE/S = 1 YES ARP/G = 1 BDR/G = 1 OST5 OST5x AOV - 1 NO 1 r OST7 CCSD/E = 1 CALL: MEMORY MODIFIED ENTRY ON RETURN BDR/G = 1 OSPT/G = 1 OST13 OSTlOx T1R2/G = 1 S/E = 1 OSCU/E = 1 OSCG/E = 1 X2 = 1 OTA/G = 1 KB/G = 1 ADD5/E = 1 OST11 0ST2y NO BLR/G = 1 OSPT/G = 1 "?>ST10 OSTIO OTA/G = 1 ADD5/E = 1 T1R2/G = 1 OST8 1 r OST13a CCSD/E = 1 CALL: MEMORY WRITE ACCESS "° » OSC8/E - 1 OSCG/E =» 1 X2 - 1 OTA/G ■ 1 KB/G » 1 ADD5/E » 1 OSTlU 0ST2y OST15 T1ST/G = 1 ROSt' = 1 YES DUMMY CP 0ST19 RWRP/S = 1 YES SCSS/S = 1 WAIT FOR OV/UV LOGIC OST16 OS ENTRY - Control Point Flow Chart U.5.1.3 SCR MOD Control Logic The SCR MOD sequence, whose flowchart is shown at the end of this section, is used to change the value of the SCR and to pro- vide corrections to PR#13 in the case of SCR underflow or overflow. There; are three control signals, S/E, X2 and WAIT which are used for control of the sequence. Signals X2 and CS are global to the sequence. When S/E is 1, the negative constants- in the 5 hit Adder Con- stant Generator are enabled. Thus S/E must be held at 1 for the duration of the sequence if decrementing of the SCR is desired and at if incre- menting is desired . X2 must be turned on if it is desired to modify the SCR by two cell sizes instead of one. This is really just another signal to the 5 ti Adder Constant Generator. In actual use however, it is often turned on by a calling control point for an OS READ Operation. This causes the OS REAL sequence to read out the next-to-the-top cell in the OS instead of the top cell. WAIT is a special control signal which is set to 1 in cases wher it is undesirable to adjust PR#13 in case of SCR underflow or overflow. Th; situation will arise whenever iterim data is being stored in either the DR; or AR, which must be used to modify PR#13, or in a case in which the SCR is only being moved temporarily and will be moved back to its original pos- tion almost immediately. Thus if the WAIT signal is on and an underflow c overflow condition occurs, a special flip-flop, DECPR, will be set and PR#13 will be untouched. This will enable the calling sequence to know that PR#13 should be adjusted, if desired, as soon as the DR and AR can be used again. The WAIT signal is often turned on before an access to OS READ or OS WRITE is made. Note that in 0ST23 a check for wraparound in PR#13 is made. If there is an adder overflow, the Operand Stack Bounds Error flip-flop i' set (see Section h. 5.1.1 for further details). 8/25/69 Section U.5-1.3 - l/l / SCR \ I MOD J SCA/G = 1 KB/G = 1 ADD5/E = 1 ROSF = 1 OST20 YES OST20x CINJ = 1 T1SC/G = 1 CKOF/E = 1 OST21 NPR13/S = 1 PRP/G = 1 BDR/G = 1 0ST21x 0ST22 ADD/E = 1 ADDO/N = 1 ADD1/N = 1 YES SDCPR/S = 1 0ST21y RWRP/S = 1 M32/E = 1 CINJ = 1 NO 0ST22y SWRP/S = 1 P32/E = 1 FLPR/N = 1 WPRV/E = 1 AKP/G = 1 NPR13/S = 1 0ST23 0ST23x (RETURN j SCR MOD Sequence Control Point Flow Chart 1+.5.1.U OS READ Control Logic The OS READ sequence is used to read data out of the OS hardwai registers into the LR (and DR in the case of a double word cell). There are two control flip-flops, NWTOS and STOR, and one control signal, NEG, which must be set prior to starting the sequence. In addition, the WAIT control signal for the SCR MOD sequence may also be turned on if it is necessary to postpone any possible manipulation of PR#13 (e.g. it may be necessary to use the DR or AR for temporary storage during the operation of OS READ; if the WAIT inhibit were not on and SCR MOD created a "wraparin on the SCR, then PR#13 would be incremented by 32 and the DR and AR conte',: would be destroyed in the process). STOR is used to indicate that the SCR will not be permanently : changed by the OS READ sequence. Therefore if wraparound occurs during ) SCR MOD sequence no change in PR#13 is necessary since it would only have to be changed back at the end of the OS READ sequence. STOR is used to - activate the WAIT signal during SCR MOD if the WAIT signal has not been , turned on already. It also is used to decide if the SCR should be incre- mented back to its original position at the end of the sequence. NEG is set to one if the data is to be read out of the OS in 1 complement form. Otherwise it is set to zero. NWTOS (no write from the OS) is set to one for the special cat when the data from the OS is only to be placed on the distribution bus ai not loaded into the LR. This case will only occur for non-double word cells and for STOR = 0. This causes a complication in task 0ST32 since IIWTOS is one, the task must remain on until after the OS READ sequence h; returned to the calling logic. In order to realize 0ST32 the design shown in Figure h . 5.1. k is used. Note that it is a more or less standard control point except that the output of the delay circuitry is not fed directly back to the U/25/69 Section J^- 5.1-U f/3 SCT2/G OSP/G OSPT/G OSPF/G BLR/G RETURN *A ( TO NEXT STAGE Figure k.5.1.k - Control Point 0ST32 7/15/70 Section U.5.1.U - 2/3 control point flip-flop. Instead it is fed to some decision logic which causes a return without resetting the control point if NWTOS = 1. If NWTOS = and OSRDSTRT = 1 then the control point is reset and the sequence continues. The need for OSRDSTRT may not be obvious. The reason it is used is that if NWTOS = 1 (and thus the OS READ sequence returns withou resetting the control point), the 0ST32 task signal will remain on so that the calling sequence can use the data on the DB. Eventually the calling sequence will have to reset OST32 in order. to use the permuter for other things. This is done by turning on RNWTOS/S which resets NWTOS and also resets 0ST32. When NWTOS goes to "0" the advance signal to the next stage after 0ST32 would be turned on (a highly undesirable effect) since the output of the delay circuit is still on. However by AND'ing OSRDSTRT to these signals we insure that the advance out signal will only be propagated in the case where the OS READ sequence is activi A further word might be said about RNWTOS/S. Before calling OS READ the calling sequence will ordinarily have to reset the NWTOS flip-flop if it desires NWTOS to be '0'. Oftentimes, the setting or resetting of a control flip-flop such as NWTOS is performed using the same calling control point flip-flop which actually initiates the sequence. In the present case, however, this must not be done since to do so would cause 0ST32 to remain in a reset condition for the whole sequence. This would obviously cause a severe error in the OS READ operation. If NWTOS must be reset before calling OS READ, it must be done prior to the actual call. In control point 0ST27 it should be remembered (see Section 2.3.1.2 on the OS Constant Generator) that the X2 signal is turned on in order to allow the generation of a constant directly from the contro] and not to multiply that constant by two. Thus when OSCU/E is used witt OSCG/E and X2, the constant appearing on the K bus is +h, not +8. 7/2/70 Section k.^.l.k - 3/3 RDCPR/S = 1 0ST30 YES WAIT = 1 0ST3DC S/E = 1 CALL: SCR MOD OST31 SCT2/G = 1 OSPT/G = 1 OST32 OST32X YES YES OSPF/G = 1 OST32Y BLR/G - 1 SCA/G = 1 KB/G - 1 X2 = 1 06CG/E = 1 OSCG^/E = 1 ADD5/E - 1 T1R2/G = 1 BDR/G - 1 OST33 OSPF/G ■ 1 OST33X OSPT/G - 1 Operand Stack - OS READ Sequence Control Point Flow Chart I*. 5-1. 5 OS WRITE Control Logic The OS WRITE sequence is used to fill the OS hardware registers with data which has previously been loaded into the. LR (and DR in the case of a double word cell). There are no control signals or flip-flops for the OS WRITE sequence itself. However the WAIT control signal for the SCR MOD sequence should be turned on if the OS WRITE sequence is returning the SCR to a previous position from which it was moved while the WAIT signal was on. Specifically, if the SCR is decremented with the WAIT signal on (because it will shortly be incremented back), then the WAIT signal must also be on when the SCR back incrementation is done. The OS WRITE sequence itself is very straightforward. 8/1/69 Section U.5-1-5 - 1/1 \ WRITE J SCT2/G ■ 1 LRP/G « 1 OSS/S = 1 DBOS/G « 1 RSD/E » 1 OSTUO CSD NO li\ ™ r DRP/G = 1 X 5 • DBOS/G = 1 / RSD/E = 1 SCA/G « 1 KB/G = 1 OSCG/E = 1 OSCU/E = 1 T1R2/G = 1 X2 = 1 ADD5/E = 1 ^ OSTUl OSTUlx 0STl*2 Operand Stack - Basic Operation Sequences OS WRITE Control Sequence 4.5.2 Supplementary OS Sequences 4.5.2.1 Supplementary OS Sequence Descriptions The Supplementary OS sequences consist of OS CLEAR and OS INITIAL which are used, respectively, to clear out the OS hardware registers by storing them in core memory and to partially load the hardware registers when the top of the OS is moved by changing PR#13. In order to understand the need for these sequences several possibly dangerous situations should be considered. For example, as was previously discussed (Section 2. 3), the Operand Stack operates in the area defined by PR#13- However, at any given time an indeterminant number of bytes of the OS are actually stored in the fast registers of the TP. Thus' if a programmer were to use PR#13 to access a cell in the stack directly (i.e. not through an Operand Stack primitive instruction), he might get invalid data if the cell were actually in the TP and not in core. Another problem arises in the situation in which the programmer wishes to change the location of his Operand Stack (i.e. modify PR#13). In this case the TP fast registers must be cleared of any valid Operand Stack data they may contain before the stack is "moved" and after-' wards the SCR and 0STR must be initialized to the new 0S position. A change in location of the OS may be effected either by changing the PR's value or its associated segment name, but not by merely storing the value of PR#13 Finally, if during an imprimitive instruction, the name of PR#1 is permuted, we have the same type of situation as that in which the con- tents of PR#13 are modified, i.e. the location of the OS will change. Th in this case, too, the TP registers must be cleared and initialized. The various occurrences of these situations can be broken down into four types : b/25/69 Section 4.5-2.1 - 1/5 1) Changing PR#13 by a PR Modification; in this case a check is made at the beginning of the sequence to see if PR#13 is the one being modified. If it is, the OS is cleared and the OSINT flip-flop is set. This signifies that before the OS is used again it must be initialized. The initializa- tion is usually done at the end of the instruction if not before. 2) Name Permutation of PR#13: if the name of PR#13 is to be changed by an imprimitive instruction, the OS is cleared and OSINT is set. At the end of the instruction, if OSINT is on, either because of a name permutation or a PR#13 modification, the OS is initialized. 3) Using PR#13 in an Address Construction: if PR#13 is used to con- struct an address (other than for adjusting the stack because of overflow or underflow), an OS clear must be performed before constructing the address. The Modified Memory Access entry skips this check; this entry is mainly used .by the control, and the control does not make accesses straight into the middle of the stack. The OSINT flip- flop is unchanged. k) Instructions with modify value or segment name of PR#13: in any of these instructions the stack must be cleared before the old value is destroyed and then initialized once the new value has been entered. 8/1/69 Section U.5.2.1 - 2/5 The 0S CLEAR sequence flow chart is given at the end of this section. The clearing operation is effected by entering the Operand Stack Overflow subsequence and executing it until the stack is empty. Note that if the top of the stack does not end on a double word boundary one or more bytes just beyond the top of the stack in core will be over- written with garbage. This may or may not matter depending on the par- ticular problem. There is also one other problem which might occur during a clearing operation. Suppose that a new Operand Stack is to be started in the middle of a double word at address a (see Figure k. 5.2.1/1 be- low). In this case the OS will be initialized with operands A and B in the hardware registers, since initialization always starts at a double word boundary. If the hardware registers subsequently become full, the A and B operands may have to be put back into core to make room. A i B core: |p-( os: |[- A i B Figure k. 5. 2. 1/1 But what if in the meantime 'B' was overwritten in core by using a PR other than PR#13? The new data in core will also be over- written and 'B' will be the final result. This is perfectly legitimate and demonstrates one of the dangers of working on data near the top of the OS without using PR#13 to do so. However, since a is the "bottom" of the OS, it would be per- fectly reasonable for some operation to modify A without using PR#13 (which would cause the stack to be cleared). In this case if the hard- ware registers were emptied into core the old value of A would be restore and a perfectly legal new value would have been destroyed. 8/19/71 Section h. 5.2.1 - 3/5 There appears to be two solutions to this problem: l) all newly- formed Operand Stacks should begin on double word boundaries, or 2) there should always be a 1 double word buffer between the beginning of a new 0S and previous block of data in core. Either of these would get rid of the problem for new stacks but the programmer must still be careful when he tries to manipulate data in the OS without using 0S instructions or PR#13. The 0S INITIALIZE Sequence proceeds according to the following scheme (see flow chart at the end of this section): 1) When the new value for PR#13 is gated into the pointer register, its low order 5 bits (which are to be found on the low order bit positions of the DB ) are simultaneously gated into the Stack Control Register (SCR). The high-order 2 of these 5 bits are also placed into the Operand Stack Top Register (OSTR). Thus the SCR defines the first empty cell in the Operand Stack to be the one whose address is the new PR#13 value. The stack full flip-flop (OSF) is set to 0. 2) If the low order 3 bits of the SCR are "000", the initializa- tion is complete without further action. This means that the initial top of the Operand Stack was on a double word boundary and thus after stack initialization, the fast registers of the 0S are empty. 3) If the low order 3 bits are not equal to "000", the double word in core starting at the double word boundary given by PR#13 (with the low-order 3 bits set to zero) is loaded into the Operand Stack fast registers starting at the register double word given by 0STR. In this case, the initialized "hardware" stack contains between 1 and 7 valid Operand Stack bytes located between the positions of the 0STR and the SCR. In actuality this may or may not be real 0S data depending on whether the new PR#13 value represents the continuation of an old 0S or the start of a new one. At any rate this concludes the initialization sequence. Figure 4.5.2.1/2 shows two examples of stack initialization. V25/69 Section k. 5.2.1 - k/5 NEW PR -#13 VALUE NEW SCR VALUE NEW 0STR VALUE 1 001 101 10,1 1001000 10 I ^S Ll t I I I I I I I I ' ' I ' ' ' ' oo 01 A. 0STR ' *SCR 10 II No data in 0S fast register NEW PR 9*13 VALUE NEW SCR VALUE NEW 0STR VALUE 001 101 I 0.1 1001 I 10 1 110 I |,l,l lll |X|X| X|X|X,X,-|-| i i I l I i l I I I l l I 1. jl 00 01 J 0STR I SCR 10 II 6 bytes of valid data in 0S fast registers Figure k. 5.2.1/2 - Operand Stack Initialization Examples 8/12/69 Section h. 5.2.1 - 5/5 OSTR= SCR\raS note.)' CS2C := CALL: 0S OVER- FLOW ENTRY on return YES CALL: OS OVERFLOW ENTRY on retUrn NOTE: In data transfers in which the registers involved are not the same size, only those bits in the larger which have corresponding bit positions in the smaller are transferred. In equality only the common bit positions are compared. Operand Stack Clear Sequence Flow Chart Section k. 5-2.1 P. 1/2 SCR := PR (13) 0STR:= PR(13) OSF = (see note) YES DB := PR(13) INHIBIT RIGHT 3 BITS DR := DB SET PRSN SELECT MST0R := cell size :=d call: MEMORY MODIFIED ENTRY on return SCR:= 0STR (see note) CALL: 0S WRITE on return SCR:= PR(13) (see note) NOTE : In data transfers in which the registers involved are not the same size, only those bits in the larger which have corresponding bit positions in the smaller are transferred. In equality only the common bit positions are compared. Initialize Sequence Flow Chart Section k* P. 2/2 k. 5.2.2 OS CLEAE Control Logic The OS CLEAR control logic is very short "but slightly confusing at first since it is highly overlapped with the logic from the OS ENTRY sequence. If OSC is 1, the Sequence returns immediately since the OS has already "been cleared sometime previously. This check may be redundant in many cases because there have been so many changes in this logic that not all of the sequences have been updated to the latest changes. However if OSC = 1 and if the high order 2 bits of the SCR and the OSTR are not equal, or if equal and the OS is full, then the overflow section of the OS ENTRY sequence is executed, beginning at control point 0ST1. Note that this sequence will be continually executed and the OSTR i incremented until these bits are equal. Next the low order 3 bits of SCR are checked for zero, and if they are not the overflow sequence is executed in final time. Finally, OSC is set to 1, Then the sequence returns. 3/16/71 Section h. 5.2.2 - l/l YES YES OSTl+3 call: os overflow on return call: os overflow on return OSTU5 SOSC/S = 1 (return ] Operand Stack - Supplemental Operation Sequences OS CLEAR Control Step Flow Chart Section k.f- P. l/l U. 5- 2. 3 OS INITIALIZE Control Logic The OS INITIALIZE sequence is used to load up the hardware Operand Stack in the TP and initialize the SCR and OSTR whenever a new value is loaded into PR#13. There are no control flip-flops to set prior to entering this sequence. It should he noted that in the memory sequence call the cell size selector is set to the control signal selection. Therefore any sequence which uses OS INITIALIZE must reset the cell size selector after the return. 8/1/69 Section U.5.2.3 - 1/1 ADD5/E = 1 BDR/G = 1 CCSD/E = 1 IB36/E = 1 IB37/E = 1 IB38/E = 1 LRP/G = 1 OTA/G = 1 RMSR/S = 1 SCSC/S = 1 SNS/G = 1 T1SC/G = 1 OST52 CALL : Memory Pre-Incr. Start on return r OST53 CALL; OS WRITE u OST55 dbst/g = 1 NPR13/S = 1 PRP/G = 1 Supplementary OS Sequences OS INITIALIZE Control Step Flow Chart k,6 Interrupt Sequencing The TP must be able to handle two types of interrupt conditions local interrupts and distal interrupts. Local interrupts concern con- ditions originating within the TP or as a direct consequence of a TP command to the AU or PAU. These interrupts are also called traps. Examples include bounds overflow, loss of significance in a floating point AU operation, or an illegal plane address in a PAU instruction. Distal interrupts are caused by some external unit or processor and are generally routed to a TP through the interrupt unit. Examples of this type include inter-processor communication (i.e. SLEEP and WAKE commands), I/O interrupts, etc. The purpose of this section is to describe the operation of the TP when it is confronted with one of these two types of interrupts. In general it must record the particular type of interrupt which has occurred and any pertinent data which might be needed to handle it. The TP must then save its present status so that the current process can be resumed at a later time, and finally must transfer control to the sys- tem Interrupt Handler. 8/19/71 Section U.6 - 1/1 INSMfl'l := LR INSM(2) := DR INSM(3l :=PR(0) DR: = PRSNR(O) INSM(10 :=FR(1) PL2/E := 1 LR:= PRSNR(l) MERGE DR— LR INHIB. BYTES 0, 1 INSM(5) INSM(61 INSM(7^ INSCT := 7 INICT := = LR = SBR = AR on entry: INSCT = 1 INICT = INSM(lNSCT) : = INPUT (INICT) INSCT :=INSCT+1 INICT :=INICT+1 YES on return CALL: INCREMENT and CHECK SEQ. PRSNR(l) :=0 PRSNR(0") :=0 DR : = (INT. LEVEL)*8 YES INICT := LNSM(INSCT) IB MSTOR := CELL SIZE= H CALL : MEMORY SEQ. MODIFIED ENTRY on return CELL SIZE=H CALL: MEMORY READ DR := AR MSTOR := 1 CELL SIZE= D CALL: MEMORY SEQ. MODIFIED ENTRY LR:= INSM(INSCT) AR:= DR+8 INSCT := INSCT+1 DR: = INSM(INSCT) CELL SIZE= D CALL: MEMORY WRITE INSCT :=INSCT+1 DR := AR INTERRUPTNJJO YES PR(O) := (INTER. LEVEL 1*8 PRSNR(0): = NAME OF INTER. HANDLER SEGMENT Interrupt Sequence Flow Chart Section k. 6. 1.3-1 k.6.1 Local Interrupts Local interrupts are generated within a processor and are handled within the processor in. which the interrupt condition occurs. Examples of this type of interrupt are: illegal operation, arithmetic overflow, illegal access, segment or page missing, etc. (see figure k.6.1 for a full listing). The IU does not handle this type of interrupt, 6/18/71 Section k.6.1 - 1/2 TP Interrupts: MNT - PNT - DNT - TRP - BOV - ILAC - PAR - SUF - ILI - AOV - ASE - ILEX - PVV - Page Map Not There Page Not There Data Not There Trap Bounds Overflow -\ J Illegal Access Parity Error Stack Underflow Illegal Instruction Adder Overflow Available Illegal EXIT Privilege Violation for Segment and Segm Name Table AU Interrupts: OV - Overflow UN - Underflow (FLT) LS - Loss of Significance (FLT) ID - Invalid Decimal (BCD) PAU Interrupts:' PAUI - PAU Interrupt (type of interrupt, i.e. bogus result will be determined by Supervisor from a halfword of data pushed into the OS] EN Interrupts: ILAD - Illegal Address PAR - Parity Error Figure h.6.1 Local Interrupts 8/19/71 Senti on k.6.1 - 2/2 •k.6.1.1 Local Interrupt Design Philosophy The Taxicrinic Processor has one major complication with regard to local interrupts which is not found in most CPU's, namely, that many instructions perform irrevokable changes on the process data base before the existence of a local interrupt (or trap) is determined. Thus, if an interrupt does occur, it is not possible to merely stop the execution of the instruction and after the interrupt has been satisfied to begin at the beginning. Instead the state of the machine at some mid- point in the instruction must be saved so that the instruction can continue where it left off. In the general case, this situation would require hundreds of bits simply to designate the sequence path which the instruction had taken at the time of the interrupt. Luckily, however, even though the instruction as a whole may not be restartable, there are many sequences which can be restarted if a local interrupt occurs within them. At the same time, since the TP has some flexibility in deciding when to recognize distal interrupts, it can always avoid looking for them during sequences which are "restartable". As a result, the number of possible "restarting points" can be greatly reduced since the TP will never have to return from an interrupt to any of the middle points of a restartable sequence. Thus, in the design of the TP sequences themselves, careful attention is paid to the sequences in which it is possible for a local interrupt to occur. For every such situation, every effort is made to either l) classify the interrupt as catastrophic (i.e. there will be no return to complete the instruction) or 2) write the sequence in such a manner that the interrupt will be detected before any permanent changes are made to the memory or the pointer or base registers by that sequence. If this can be done, then whenever a local interrupt is detected, a special "interrupt exit" can be made back to the calling sequence. This means that the sequence which detected the interrupt can be restarted when operation is resumed after the interrupt handling. 6/21/71 Section k.6.1.1 - 1/ 3 By going through this process at higher and higher levels of nested calls, the interrupt can be bucked back until eventually a return is made to a sequence which cannot undo a previous operation. Such a point in a sequence is called an Interrupt Point , After the interrupt has been processed, control will have to be returned to the proper Interrupt Point in order for the interrupted instruction to continue. In addition, these Interrupt Points are the only points in the control sequences where the TP looks for distal interrupts. The end result of this whole process is to reduce the number of possible machine states which must be saved in orde; to be able to restart after an interrupt. The overall operation of the TP Local Interrupt system can be described as follows: as soon as an interrupt condition is discovered during the operation of some subsequence, the normal sequence halts, sets the proper interrupt indicator bits and after making any necessary adjustments makes a special interrupt return. The sequence which called the interrupts sequence will in turn, perform any operations which may be necessary to restore its status to a stable condition and then it will make a special interrupt return. This process continues until eventually a return is made.! to a sequence which cannot undo a previous operation, i.e. an Interrupt Pol. Once an interrupt has been detected and control has reached an Interrupt Point, the hardware transfers control to the hardware Interrup Control Sequence. This sequence has the responsibility for determining the level of the recognized interrupt and for storing the information necessary for processing the interrupt in the Interrupt Storage Segment. In addition, it must save the necessary TP registers and status information; which will be needed to restart the TP when processing resumes after the interrupt has been taken care of. The information stored by the TP consists of two types: information needed to process the interrupt, and information used to restore the status of the TP when the interrupt processing has been completed. In order to keep the volume of the latter type of information as small as possible, only those registers are saved which are absolutely needed to specify the interrupt. If more registers are needed later on in interrupt processing, the procedure performing the processing has the responsibility for saving their contents. As a result, among the Pointer 6/21/71 Section 1+.6.1.1 - 2/3 Registers for example, only PR#0 and PR#1 are initially saved in the storage block. PR#0 must be used in transferring control to the Interrupt Handler, while PR#1 is used to point to the storage block itself. In addition to holding the two types of information just mentioned, the Interrupt Storage Block is also used as temporary storage by the Interrupt Handler. This is necessary since the Interrupt Handler Procedure cannot necessarily assume that any data storage other than the Storage Block itself is still usable (i.e. Available Space may be exhausted, the Operand Stack may have had a bounds overflow, etc.). The TP will load one predetermined part of this area of the Storage Block with the entry which was used in the pointer circular buffer. This allows the Interrupt Handler to replace the original pointer entry with a new pointer to a new unused block of storage. Once these storage operations have been completed, the TP has finished the operations necessary for the recognized interrupt. It is possible, of course, that more than one interrupt was present at the time the TP recognized the interrupt situation. In such cases the TP chooses the highest priority interrupt, or if there is more than one at the highest priority it will choose one of them by some deterministic method. All other interrupts will remain pending. After having stored the necessary information, the TP turns on the interrupt masks and transfers control to the appropriate processing level of the Interrupt Handler procedure. The transfer of control is accomplished by loading PR#0 with the standardized segment name for the Interrupt Handler procedure and the virtual address of the appropriate entry in the Interrupt Handler's branch table. This location will contain a branch instruction to the procedure which takes care of interrupts at the given level. At the completion of the interrupt processing, the Interrupt Return sequence reloads the necessary TP registers, the control flip-flops and sets up the interrupt return state of the machine. Then it returns to the interrupt return point. The following sections will give a more detailed description of the Interrupt Sequence and Interrupt Return Sequence. 6/21/71 Section ^.6.1.1 - 3/3 U.6.1.2 Interrupt Storage Segment Upon detection of an interrupt, it is the responsibility of a Taxicrinic Processor to store certain registers, status flip-flops, and other indications of its current state along with enough information to tell the Interrupt Handler what type of interrupt took place. The purpose of this section is to describe the Interrupt Storage Segment (which contains space for this information), and to explain how informatl, is loaded into and out of this storage area. The Interrupt Storage Segment is unique for each task in the Illiac III system. Although the length of this segment can vary from one task to the next, depending on the expected amount and type of interrupt activity, the basic format is the same. As shown in Figure h. 6. 1.2/1, the Interrupt Storage Segment is divided into three basic areas: the status area, the pointer circular buffer area and the storage block area. The status area is divided into entries corresponding respective to the various interrupt levels. Each entry consists of a Last Filled Block control double word (CDW) which indicates the status of the pointer circular buffer for the corresponding interrupt level. It indicates the pointer in the circular buffer which points to the next block to be fille. with interrupt information at that interrupt level. At the end of the st: area there is, in addition, an available space format entry which is used by the Interrupt Handler in assigning storage clocks to the various cir- cular buffers. The pointer circular buffer area is also divided into sections corresponding to the interrupt levels. Each section contains one circul' buffer of pointer entries. These buffers may contain anywhere from one entry on up. The storage block area comprises the rest of the Interrupt Storage Segment and consists of storage blocks used to contain the inforirt- to be stored during interrupts. These blocks, which are controlled by t\ standard available space techniques, are shifted on to queues, processed; and eventually returned to available space. 6/21/71 Section U.6.1.2 - 1/6 Last Filled CDW Last Filled CDW • • Last Filled CDW Avail. Space Format * ^\ Level 1 Level n Level 1 Level 2 S Status Area < Level n Pointer Circular Buffer Area Storage Block Area -/ Figure h. 6. 1.2/1 Interrupt Storage Segment Structure 7/15/70 Section ^.6.1.2 - 2/6 As far as using the Interrupt Storage Segment is concerned, all storing of interrupt information is controlled through the control double words. The CDW's have the format shown in Figure k, 6. 1.2/2. The rightmost halfword contains the pointer to the next entry in the corres ponding level's circular buffer. The leftmost halfword field contains the address of the beginning of the circular buffer. The second halfword contains the increment field. The third halfword contains the beginning address of the first byte after the last entry in the corresponding level's circular buffer. Given this format, the process of finding storage for the interrupt information at a given level interrupt is quite simple (refer to Figure h. 6. 1.2/3). First an access is made to the appropriate last filled CDW. . The pointer thus obtained is then incremented by the length of an entry in the circular buffer (the increment field of the CDW). This new pointer value is used as the address of the pointer to the block into which the interrupt information is to be stored. If the new pointer value does not equal the maximum allowed address, it is stored in the pointer value field of the control doubleword. Otherwise, the initial value from the leftmost halfword field is stored in the pointer value field in the control word. An important point to note is the case of the Supervisor which can in fact be running on several TP's at one time. In this case, or in general in the case of any task which may run on more than one TP at a time, a problem of processor interference during the interrupts occurs. If two "Supervisor" TP's (i.e. TP's on which the Supervisor is running) both have interrupts at the same level at the same time, they could end up filling the same storage block in the Interrupt Storage Segment. To avoid this situation, it is necessary for the control word manipulations to be performed during only one Exchange Net access. Since the Exchange Net does not allow more than one TP to access a given core box at one time this restriction will ensure that by the time the second TP gets to the Last Filled Block control double word, it will have been updated to reflec the use of one of the storage blocks by the first TP. The only operation 21/71 Section k. 6. 1.2 - 3/6 Initial Value Increment Maximum Value Pointer Value Figure 4.6.1.2/2 Control Double Word Format 7/15/70 Section h.6.1.2 - k/6 CDW: Initial Value Increment Maximum Value Pointer Value ^ 10 11 12 Figure U. 6. 0,2/3 Use of CDW to Obtain an Interrupt Storage Block 7/15/70 Section U.6.1.2 - 5/6 necessary on the part of the first TP is that it must not let go of the Exchange Net until after it has updated the pointer entry and replaced it. This is done using the logic of the Increment and Check (INCK) instruction. 6/21/71 Section U.6.1.2 - 6/6 U.6.1.3 Interrupt Sequence h. 6. 1.3.1 Interrupt Sequence Description The purpose of the Interrupt Sequence is to store the Interrupt Status of the TP in the Interrupt Storage block and to prepare the TP for a transfer. In order to load the storage "block it is necessary to make several memory accesses, first of all to determine which block to fill and then to actually fill the block. However, since the original interrupt may occur in the middle of a memory access or at some other point where all of the registers contain data which must be saved, a method must be found for saving this data while making accesses to determine the interrupt storage block to be used. The means which was decided on was an Interrupt Storage Memory internal to the TP. The IC interrupt storage memory is made up of l6, 36-bit words of memory. It is arranged on 8 cards in such a manner that it can collect the interrupt information simply by pulsing the proper counter at the proper rate. Once this information is stored, the TP can then make use of the registers which originally contained that information to access memory, find the interrupt block and then read out the saved interrupt information from the IC interrupt storage memory into the core memory interrupt storage block. The Interrupt Sequence itself is reasonably straightforward. Referring to the flow chart at the end of this section, it can be seen that the initial steps consist of loading the Interrupt Storage Memory with the contents of various registers. Note that the zeroth entry of the interrupt storage has already been filled by the sequence which detected the interrupt. The order in which the registers are stored is fixed so that those registers which are needed to merge and build up th< more complicated data (i.e. the LR and DR) are saved first. Note also that the IR is not stored until after the miscellaneous data bits. Thi: is necessary because on an interrupt return the IR will be used to restce the TGR and mnemonic byte data and can thus not be loaded with its re- stored information until the completion of this operation. Once the interrupt storage memory is loaded, the next task is to determine the address of the Interrupt Storage Block to be used 8/19/71 Section k. 6. 1.3.1 - lA to contain this interrupt information. Figure k. 6. 1.2/1 depicts the structure of the Interrupt Storage Segment while figure h. 6. 1.2/3 shows a circular buffer of interrupt block entries. In order to access the Interrupt Storage Block the control sequence first loads PR Segment Name Register #0 with zero, i.e. the segment name of the Interrupt Storage Segment and the DR with the number of the interrupt level multiplied by 8. This latter quantity is used to determine the address of the control double word for the interrupt level of the current interrupt. During the loading of PRSNR(O), the PR Segment Name Selector Register is set to select PRSNR(O) so that when the Increment and Check sequence is entered, it will process the control DW within the interrupt storage segment corresponding to the current interrupt level. Note that prior to loading PRSNR(O) with the segment name of the interrupt segment (i.e. "0"), PRSNR(l) is loaded with the same name. This is necessary since PR#1 will be needed to access the interrupt block once control is passed to the Interrupt Handler Procedure. When the Increment and Check sequence returns, the DR will contain the virtual address of the entry in the circular buffer for the interrupt level of the current interrupt. The sequence accesses this halfword entry to obtain the virtual address of the interrupt storage block. This address is stored in PR#1 and the DR and then the Modified Entry of the memory sequence is used to calculate and check the 2^-bit actual address which eventually is put in the AR, right justified. Since each access to the Interrupt storage block will be on the same page, the calculation of the core address and all of the validity checks need only be performed once. Thus we can save a great deal of time by performing the address calculation before entering the memory storage access loop. Once control reaches the memory storage access loop, successive words from the IC interrupt storage memory are loaded into the LR and DR 6/21/71 Section U. 6.1.3.1 - 2/h and then written into the core memory. The format for the interrupt storage block showing the location of the various interrupt information is given in figure 4.6.1.3.1/1. Note that a check is made at every point in the sequence where an interrupt might he detected due to memory or exchange net failure. If at any time such an interrupt occurs, disaster has struck and about the only thing which can be done is to turn on a light and start some bells ringing. 6 /21/71 Section k.6.1.6.1 - 3A BLOCK POINTER FOR US£ BY SYSTEM 8 SEGMENT NAME VIRTUAL ADD. LR 16 DR PR#0 24 PR#1 PRSNR# PRSNR#i 32 SBR AR 40 TGR INST. MNEM. CONTROL FF STATUS 48 CALLING CONTROL POINT STATUS 56 PRIORITY LEVEL INTERRUPT TYPE MISC. STATUS 64 IR Figure U. 6.1. 3.1/1 Interrupt Storage Block Format 8/10/71 Section k, 6, 1.3.1 - h/k 1+.6.1.3.2 Interrupt Status Collection Logic The Interrupt Status Collection Logic is the logic used to gather up the data which is to he stored in the IC Interrupt Storage Memory and to gate it to the input lines of this memory. In j general, there are two levels of saving which might be involved in an "interrupt" (in this case using the word in a very broad sense). the higher level there is the TP status necessary to restart the interrupted task . At the lower level there is the TP status which is necessary to restart the interrupted instruction. The distinction be these two levels will now be explained. In general there is quite a bit of information which must t| stored when a task is removed from a TP. This basic information is stored in the Task Control Block when the task is inactive. Although it is true that many interrupts will eventually result in having a given task taken off of the TP, this is not always true. In these latter cases it would be quite inefficient to store all of these quantities if they are not going to be used. Therefore it was decide that the interrupt sequence itself would only save that information ' | which was necessary to describe the interrupt and to restart the particular instruction which was interrupted. If it later becomes obvious that the task is going to have to be taken off the TP, then the Supervisor is responsible for saving the rest of the task informri ■ in the TCB. On an interrupt return the procedure will be reversed. If the task has been inactivated part of the job of the supervisor reactivation procedure (see Section 5.6.5.2) will be to reload the necessary registers from the TCB before returning control to the tas In order to simplify the process of collecting the interru: status bits and registers which must be saved by the hardware interrupt sequence, each input bit line to the interrupt storage memory of the TP has been attached to an IC multiplex chip, as shown in figure U, 6|L,3. Thus by hooKing the various input lines of the multiplex chip to the various status bits, the status bits can be gated to various words i the interrupt storage memory, by counting up on the multiplexor and memory address counters simultaneously. 6/21/71 Section U.6.1.3.2 /3 '_-. SN74151 DBB1 FF37 FF73 FF109 FF145 FF181 FF217 FF253 272 DBB36 FF72 FF108 FF144 FF180 FF216 FF252 FF288 SN7493N INTCNT/E COUNT H*TO INTERUPT MEMORY, BIT LINE 1 34 SN74151 34 Do D, D 2 D 3 D 4 D 5 D 6 °A 7 B C -►TO INTERUPT MEMORY, BIT LINE 36 Figure k. 6. 1.3. 2/1 Interrupt Status Collection Logic 7/15/71 Section 4.6.1.3.2 - 2/3 Note that the zeroth input line of each multiplex chip is attached to the DBB bus. This allows registers to he gated into the interrupt storage memory through the Permuter. Note that since the memory address counter and the multiplex counter are controlled independently, an arbitrary number of full word registers can be stored in the interrupt storage memory before using the multiplexor counter to store the various miscellaneous bits. The miscellaneous bits being stored consist of status flip- flops, small registers such as the TGR, several types of interrupt information such as priority level, type of interrupt, etc., and the status of those calling control points which may be active before entering the Interrupt Sequence. This latter information must be saved in order to be able to determine the proper return paths when processing resumes after the interrupt has been handled. It is the calling control point which indicates which particular sequence made the call when it is time for the called sequence to return control (see Appendix U.A). 6/21/71 Section 1+.6.1.3.2 - 3/3 k,6,l.k Increment and Check Sequence 4.6.1.4.1 Increment and Check Sequence Description The Increment and Check Sequence is used to update control double words of the format shown in figure 4. 6. 1.4.1 below: Initial [ Increment Value Value Maximum Value Pointer Value Figure 4. 6. 1.4.1 Control Double Word Format The sequence accesses the control double word at the virtual address which was previously stored in the DR. The PR Segment Name Selection Register must also have been set before entering the sequence. When the data returns from the memory unit the sequence increments the pointer value field by the contents of the increment value field without releasing the Exchange Net. This insures that no other TP will be able to access the control double word until the sequence has completed its operations. When the incrementation has been completed, the sequence checks the incremented value against the value in the maximum value field. If the incremented value does not equal the maximum allowed address, it is stored back in the pointer value field of the control double word. Otherwise, the initial value field is loaded into the pointer value field. In either case the original pointer value field is loaded into the DR right justified and the EQ flip flop is set according to the status of the test. This sequence has several uses. First of all, it is used for controlling the Interrupt Storage Segment circular buffers. In this case, the initial and maximum value fields denote the beginning and end of the circular buffers and the increment value field is set to two, i.e. the length of the halfword entries in the circular buffer. In the general case, when used as part of the INCK instruction, the sequence can be used to control arbitrary buffers using the same general format. 6/21/71 Section h.6.1.k - 1/2 Secondly, the sequence ("by means of the INCK instruction) can "be used in controlling "critical sections" so that only one programmer will utilize a section of core at a time. In this case, a control double word is set up for each such "critical section". To be used in this manner, the pointer value field of the double word is originally set to one, the increment field is zero, the initial field is and the maximum field is 1. When a processor wants to use a critical section, it first per- forms an INCK on the control word for that section. If there is no processor in the section, the pointer value will be'l and after being incremented by it will equal the maximum value field, thus causing the initial value of to be ret-uosaed to the field. Then after testing EQ anc discovering it is on, the TP can begin processing in the critiaal section. Now suppose a second TP wants to process in this same area before the first TP is finished. In this case it will also perform an INCK. This time, however, the new pointer value, after being incremented by 0, will still be zero and will thus not be equal to the maximum value field of 1. When this second TP checks the EQ indicator it will be off and thus the second TP will have to "go to sleep" for awhile. Eventually the first TP will finish its processing and at this point it will set the control word pointer value back to 1. Thus eventually when the second TP again checks the control word, it will be allowed to use the "critical section". Note that the biggest problem with this procedure is that it relys on the "honesty" of a programmer to check the appropriate entry before using a "critical section" and also to reset the entry when it is finished. A third use of the sequence is as a means of controlling loops. However, this will only work if it can be guaranteed that the pointer value will eventually equal the maximum value exactly. A flowchart for the Increment and Check Sequence is given at the end of this section. 6/21/71 Section k.6.1.k - 2/2 MERGE DR— LE IMHIB. 0, 1 DR := AR YES EQ := 1 PL2/E DR EQ := 1 := AR := (INCREMENTS DR contains virtual and / address. PRSNR8 Is set. CHECK MSTOR := 1 CELL SIZE=DW CALL: MEMORY SEQ. MODIF. ENTRY on return ADDO/N = 1 ADDl/N = 1 DB := LR AR := DR+DB DR := SBR DB := +6 AR :- DR+DB MERGE DR— LR LNHIB. BYTES 2, 3 INTERRUPT no YES XNHOLD := 1 CALL: MEMORY READ on return SBR := AR AR := DR PL2/E := 1 DR := LR CELL SIZE = H CALL: MEMORY WRITE INTERRUPT T NO YES Bj DR contains original / pointer value right Justified. INCREMENT and CHECK Sequence Flow Chart Section k.6.1.k.l U.6.1.5 Interrupt Return Sequence h. 6.1. 5.1 Interrupt Return Sequence Description The purpose of the Interrupt Return Sequence is to restore the status of the TP to the previous state indicated "by the Interrupt Storage Block whose initial virtual address is given in the DR. The PR Segment Name Selector Register must be set before entering the sequence. The sequence also returns the Interrupt Storage Block to the Available Space area. The operations involved are shown in the flow chart at the end of this section, and are approximately the reverse of the operations performed by the Interrupt Sequence (section ^.6.1.3.1). The first task is to load up the Interrupt Storage Memory from the Interrupt Storage Block. Then the Interrupt Storage Block is placed back on the Available Space list using the core memory version of AS RESTORE. The next task is to restore the status of the various registers. The restoration of the LR, DR, PR(O), PR(l), SBR and AR are very straightforward. In the case of PRSNR(o) and PRSNR(l), each register is only 2 bytes long so that the output from the corresponding interrupt storage memory word is gated out twice and permute in the case of PRSNR(l). The eighth word in the interrupt memory contains the original contents of the TGR and the mnemonic register. These quantities are gated into the IR from which position the respective registers can be loaded in the conventional manner. The remaining status bits are then restored using a counter setup similar to the multiplexing on the input to the interrupt storage memory. This logic is described in detail in section h. 6. 1.5. 2. Note that before loading the status bits, all of the calling control points are reset. Then when the calling control point status is read out, these control points are set according to the status bits which were saved when the interrupt was detected. In particular the calling control point which first called the Interrupt Sequence at the original interrupt point will be set. This means that when the Interrupt Return sequence has completed its operations, it can return to the 6/21/71 Section 1+.6..1.5.1 - 1/2 .proper interrupt point simply by returning as if it were the end of the Interrupt Sequence. Thus every calling control point which calls the Interrupt Sequence will have its return signal line coming from the Interrupt Return sequence. The last operation in the Interrupt Return sequence is to restore the status of the IR. Then the sequence returns to the Interrupt Point to take up operations where it left off previously. 6/21/71 Section U.6.1.5.i - 2/ 2 DR contains address of Interrupt Storage Block MSTOR := CELL SIZE=D CALL: MEMORY SEQ. MODIFIED ENTRY YES INSCT DR AR := := AR :=DR+8 CELL SIZE=D CALL: MEMORY READ INSCT :=INSCT+1 AR := DR+8 insm(insct) :=l insct:=insct+.i DR := AB INSM(lNSCT):=D i LR := SBR DR := n+1 WHERE n IS THE NUMBER OF INTERRUPT LEVELS. TGF := IR MN := IR CLEAR CALLING CP'S INSCT := 8 INOCT := D SBR AR IR := INSM(6) := INSM(7) := INSM(8) PRSNR(O) :=INSM(5) PL2/E := 1 FRSNR(l) :=INSM(5) LR := INSM(l) DR := INSM(2) PR(0) :=INSM(3) PR(1) :=INSM(*0 INSCT :=INSCT+1 IN T Ai u Figure k.J.2. 5 Technique for Halting Sequences 3/2U /TO Section U.7-2.5 - 2/ k. 7.2.6 Reset Sequence Halt The RSH command turns off all of the hits in the sequence halt selector. This means that no sequence operations will be stopped in the future unless one of the selector hits is turned on by a subsequent SSH command. 8/21/69 Section k.1.2.6 - l/l U . 7 . 2 . 7 Execute Sequence The EXEC command executes the sequence specified by the 6-bit operand field in the command. The last byte of the data field is used to supply the desired states of the control signals and flip-flops for the sequence to be executed. The table in Figure k. 7. 2.7/1 gives the order of "parameters" for the various sequences. This field is decoded using the same logic as in the Set Sequence Halt command. In this case however, the decoded output is used to activate a calling control point to the selected sequence. When the sequence returns, the TP signals to the console that it has finished. 6/lU/Tl Section U.7.2.7 - ]2 Number Entry Point Name PARAMETERS Memory Direct Entry 1 Queue Counter Update 2 Part. Mode Add. Conver, 3 Memory Read k Memory Write 5 OS CLEAR 6 OS ENTRY 7 Overflow Entry 8 SCR Modified 9 OS Read 10 OS Write 11 Memory Modified Entry 12 AS Get 13 AS Restore Ik Stack PR 15 Unstack PR MSTOR POP SNAMT IMF CS2C XNHOLD XNHOLD XNHOLD DUP S/E WAIT X2 NEG WAIT WAIT NWTOS MSTOR XNHOL ASTRS ASTRS STOR Figure 4*7.2.7/1 Parameter Positions for Execute Sequence Command for Sequences in the Core Machine 6/17/71 Section 4.7.2.7 - 2/2 1+.7.2.8 Interrupt The INT- command causes the TP to react as if an interrupt of the highest priority has taken place. This console-generated interrupt is not maskahle. Therefore it allows the console to take control of a TP independent of what else is happening in the environment. The command also causes the Instruction Halt flip-flop, IHLT, to "be set so that the TP will halt as soon as it has stored all of the interrupt information and tries to execute a new instruction. The INT command is one of two console commands which will be obeyed by a TP while it is running. The other is SIH, the Set Instruction Halt command. The INT command can be used to save the state of an operating TP whenever an engineer wants to commandeer it to perform some diagnostic operation. Once this command has been issued the TP can be used in the sequence exercise mode without fear of destroying valuable information in the registers. After an INT command has been issued the console can also be used to execute the interrupted program in a step-by-step manner. In this case the Interrupt Return command can be issued without resetting the IHLT and/or MHLT flip-flops, thus causing the TP to single step on an instruction basis or a maintenance halt basis.. Eventually, if it is desired to restart the TP in exactly the same condition as prevailed when the interrupt occurred, it is only necessary to reset IHLT and MHLT and then issue an Interrupt Return command. 8/21/69 Section 4.7-2.8 - l/l 4. 7-2.9 Interrupt Return The INTRN command causes the TP to restore its registers and control points to the state which prevailed at the time of the last Interrupt command. The program which was on the machine at that time will be reactivated and allowed to continue. However since IHLT and/or MHLT may possibly be still set, the program may stop soon after it has been reactivated. If these flip-flops are off, however, the program will continue in the normal fashion. The Operating System has the power to restart a program which has been interrupted by a INT command, but only by issuing a subsequent INTRN command through the console. 8/21/69 Section 4.7.2.9 - 1/1 1+.T.2.10 Run This command allows TP operation to continue. It will reset the second stage of the instruction halt flip-flop or the .laintenance halt flip-flop if either of these flip-flops have been given a reset command. The TP will again halt at the appropriate place if any of the halt indicators are still set. If all halting conditions have been reset, the program execution will continue in the normal fashion. 6/23/71 Section i^.T.2.10 - I 1 ^•7-2.11 Load/Read Registers These LOAD and READ commands cause the designated register to either "be loaded from the data lines or read out onto them. The desired register is indicated by a 6-bit field within the command. The register assignment is shown in Figure k. 7- 2.10/1. Note that for consistency and ease in decoding, all storage which consists of blocks of registers uses the same bits for selecting which register is to be loaded or read out. These operations work by utilizing the TP Permuter logic to access the desired register. The command is decoded to select the desired register. If the command is a LOAD, the data is gated into the Permuter by means of a special input to the PR Segment Name bus, PRSNB. The PRSNB can be gated to the Pointer Register bus, PRB and then to the Permuter. The desired register is then loaded by selecting the proper output control lines in the Permuter. Note that although the PR Segment Name Registers are only 16 bits wide, the PRSNB is actually 36 bits wide (U bytes). This is necessary not only to handle the present situation, but also several other data transfers If the command is a READ the TP-Console Interface logic turns on the proper input control lines to the Permuter and then gates the DBB permuter output bus in the control section to the data lines. 8/21/69 Section h. 7.2.11 - 1/2 Code 1 2 3 k 5 6 00 001111 Pointer Register block - one of 15 registers Spare Buffer Register. 01 PR Segment Name Register "block - one of 16 registe 100 101000 101 Base Register block - one of 8 registers. Task Register. Associative Register block - one of 7 registers, 110 Operand Stack - one of 8 words 11100- 11101- Instruction Buffer Register - one of 2 words Name Registers - one of l6 - h bit registers 111100 111101 111110 111111 LR DR IR AR Figure k. 7-2.11/1 - Register Selection for LOAD and Read Commands 8/21/69 Section U.T.2.11 - 2 k. 7.2.12 Autoload The AUTOLOAD command causes the TP to initiate its autoload sequence. This involves clearing the entire TP logic and then setting up the various conditions in the TP which are necessary prerequisites for correct operation. The detailed operations involved in this sequence are fully explained in Section k.Q. Considerable care must "be taken in implementing this command on the console. Obviously, we /ant to make it nearly impossible to auto- load the wrong TP. The requirement that a processor be stopped before a console command is accepted helps somewhat in this respect. It might also be desirable to have a manual lockout so that the autoload command is not given accidently. 6/23/71 Section k.1.2.12 - l/l ^.7.2.13 Positi on The POSITION command causes a processor to send to the Engineering Console its current control point position "within the control logic. This command can only be obeyed when the processor is halted. The position of a Taxicrinic Processor is given by two items of information: the currently active sequence and the currently active control point within the sequence which was last activated. The active control point can be easily determined by having the flip-flop portion of each control point or'ed to a particular position in an n line signal array. The particular position will depend on the control points relative position within its sequence. If calling control points are excluded from the signal array, only one signal will be on at a time and the output of the array can be coded into a binary number for transmission to . the Engineering Console. ; In the actual implementation a 63 line signal array is used. Thus control points may be numbered from 1 to 63. Unfortunately as often happens, errors are found which necessitate adding extra control points in the middle of a sequence. Renumbering all the control points in such ; a case is quite difficult and may lead to much confusion. As a result the new control points are usually given a number corresponding to a "Nearby" control point but with an alphabetic character, "B" through "D" added to the end. The letter "A" is added to the end of the original control point. In order to handle these letters the signal array provides 3 additional lines for encoding letters. If the control point ends in "B" , "C" , or "D" , the indicator for that particular control point must activate the appropriate letter line as well as its corresponding position in the signal array. If no letter line is activated, the logic assumes the letter "A". These h letters are encoded into 2 bits and, wher. added to the 6 bits from the signal array, produce an 8 bit control point position address which can be sent to the Engineering Console. The determination of which sequence is the one currently active is more difficult since more than one sequence may be on at one 12/22/70 Section I*. 7. 2. 13 - lA time and we are really only interested in which one was turned on most recently. The solution to this problem for the TP was to arrange the sequences in a hierarchy based on their calling order as shown in Figure 4. 7. 2. 13/1. Sequences at each level of the hierarchy only call sequences which are at lower levels and only return to sequences at higher levels. In ' addition the sequences on any given level can only make absolute transfers of control between one another. This means that of all the sequences at any given level, only one can be activated (i.e. entered and not. yet finished) at any given time.- Thus all of the sequences at a given level can be encoded with one binary number of log^N bits instead of N bits (where N is the number of control sequences at that level) . As a result of this "level re coding", the name of the currently active sequence can be recorded by maintaining an "active" signal for each sequence and then using these signals to produce the proper states in a signal array which consists of several binary fields, one field for each level in the control sequence hierarchy. The currently active sequence will be the one indicated by the highest hierarchical level with a non-zero entry. This can be determined by programming in the Engineering Console once the status of the sequence name control signal array has been sent to it. Figure 4.7.2.13/2 shows the encoding of the sequence name signal array based on the "Basic Machine" of the TP. 6/23/71 Section 4.7.2.13 - 2/4 level: 1 234567 Level 0: Main Control Prim. Inst. Imprimitive PAU Entry PAU End PAU Field Ace. PAU Fini Final Control 0001 0010 0011 0100 0101 0110 0111 1000 Level 1; Instruction Execu- tion Sequences (8 bits) Level 2: Name Permutation 001 Phrase Process 010 OS Initialize 011 PAU Access 100 Post Op. Seq. 101 Level 3: Increment ICT 01 Phrase Seq. 10 IBR Reload 11 Level h: Exchange PR-SBR 001 Stack PR 010 Unstack PR 011 OS Read 100 OS Write 101 Level 5: OS Clear 001 OS Entry 010 OS Clear/OS Entry 011 SCR Mod 100 AS Get 101 AS Restore 110 Level 6: Memory Add. Calc. 01 Memory Write 10 Level 7: Par. Mode Add. Calc. 01 Queue Counter Update 10 Memory Read 11 Figure k. 7.2. 13/1 8/19/71 Section It. 7. 2. 13 - 3 A _|UUJ 2(- o o tn uj zz en 0) c! •H ,3 O cd a CJ •H CO pq !h O > o U oi Sh (U •H M 0) o 0) CT 1 CQ OJ m H • CM r- •H (in 8/2U/71 Section 4.7.2.13 -4/4 U . 7« 3 TP-Engineering Console Interface - Logical Design The most important goal for the design of the TP-Engineering Console Interface Logic is that the interface be capable of operating properly even when large sections of the TP are not operating reliably. In order to do this, the interface logic must be reasonably simple and easy to repair and must rely as little as possible on other parts of the TP. Toward this end, the TP-Engineering Console Interface has been designed almost exclusively with combinational logic. It consists mainly of two sections: the Command Decoder and the Command Execution logic. The Command Decoder is composed only of combinational logic. The Commanc Execution logic makes use of several control points to set flip-flops anc initiate sequences in the case of the Execute Sequence command. The only part of the TP logic which must be used by the TP- Engineering Console Interface directly is the Permuter. The Permuter J and several of the data busses connected to it, must be used in order to get information into and out of the TP registers. Other than this howeve the interface does not depend on any of the TP logic sections for the interpretation and initiation of its commands. The remaining portions of this section will describe the detai. of the logical design of the interface. 8/21/69 Section U .7 ■ . 3 - l/ 1 k. 7.3.1 Engineering Console Command Decoding The Engineering Console controls the operation of the TP through cahles running to the TP-Engineering Console Interface Logic on the individual TP's. A certain number of these lines (at least 10, but possibly more) will be used for the command itself. The purpose of this section is to describe how the TP-Engineering Console Interface logic decodes the information on these lines. At present, the Engineering Console command format can be thought of as consisting of three fields: the processor /unit address field, the command field, and the "operand" field. The processor/unit address field may not be necessary if the parallel structure shown in Figure i+.T.l/l is used as the Engineering Console communication organiza- tion. However, if the series structure is used it will be necessary for the interface logic to compare this field with its own internal name, which might be represented by switch settings which can be changed at the discretion of the maintenance personnel. The logic necessary for this comparison is shown in Figure k. 7. 3.1/1. The command field itself is of indeterminate length at the present time. Given the commands presently mentioned it must be at least 3 bits long. This estimate is based on the assumption that all commands which do not utilize the "operand" field will be given the same command bit configuration and only differ in the setting of the operand bits. This field will be decoded using a full decoder on as many bits as are in the field. The six bit "operand" field is used for designating sequences in the Execute Sequence and Halt at Sequence commands and is used to indicate registers in the Load and Read Registers commands. In order to minimize the number of IC chips needed for this decoding, the field is first divided into two 3 bit fields which are decoded separately. 8/21/69 Section U.T.3-1 - lA SWL 1 BITl SWl *\ ^rv^ BITl SW2 ) BIT2 ) — ^ ^~~\> \>° r-n—S r SW2 k>— BIT2 SW3 ) BIT3 SW3 ) BIT3 ) >: Figure k. 7. 3.1/1 - Logic for Detecting Command Address 12/10/69 Section U.T.3.1 - 2/U Then the resulting two sets of 8 signals are combined pairwise in all possible combinations to produce 6k possible outputs each of which repre- sents one of the 6k bit combinations in the 6-bit field. These signals are then used to perform the various necessary selection operations which will be described in Section k. 7.3.2 A schematic representation of the decoder is shown in Figure ^.7.3.1/2, 8/21/69 Section 1*. 7,3.1 - 3A 1 2 3 4 5 6 CUO 6 CU7 CLO 6 CL7 6 ^3 48 r> 6 CDCO 6 CDC7 48 CDC56 6 CDC63 Figure h. 7- 3.1/2 - Schematic Representation of the 6-Bit "Operand" Field Decoder 12/10/69 Section 4.7-3.1 - h/h k , 7 « 3 • 2 Engineering Console Command Execution Logi c Once the command from the Engineering Console has been decoded by the TP-Engineering Console Interface, the command execution is reasonably straightforward. In the case of halt indicators, a two-stage flip-flop is used as shown in figure k. 7.3.2/1. Both stages are set to 1 by the set signal, but only the lower stage is reset by the reset signal. The upper stage is only reset upon the subsequent issuance of a "start" command, such as RUN or Interrupt Return. This technique is used in order to keep the TP from starting off as soon as the indicator is reset. It allows the console computer to pick the type of resumption to be used. In the case of the Console Interrupt all that need be done is to set the proper indicator signal. The TP Interrupt Sequence does the rest. When the Console Interrupt Return signal is given the interface logic causes the TP Interrupt Return sequence to be activated. Note that both of these commands are exceptions to the general rule that console commands should not directly use sequences in the main TP logic for their execution. This cannot be helped here, however, because of the nature of these specific commands. The Load/Read Register commands use a fairly substantial amount of combinational logic since there are many possible select signals to activate. If a LOAD or READ Register Command is detected, select signal(s) corresponding to the register indicated in the 6-bit operand field of the command are set. Then the necessary write/read signals are turned on to gate the information into/out of the register. There are many modifications to this general method, however, depending on which register is involved. For example, in the case of the PR Segment Name Register, two different sets of select signals are needed: one for loading the registers and one for reading. This is not true for the other registers blocks and arises from the slightly different organization utilized by the PR Segment Register storage block. 6/14/71 Section 14.7.3.2 - 1/k HALT2 HALT! SET RESET START SIGNALS Figure ^.7-3.2/1 Halt Indicator Logic 8/17/71 Section h. 7. 3.2/1 - 2/h Base Register selection is also straightforward. In this case the select signals from the console form one of three possible sets of signals which can be used to select the base registers. The other two sets come from the Queue Counters and the Association Logic. Operand Stack selection is a little different. In this case the operand field indicates which one of the eight possible words in the hardware stack is desired. (Note that these are hardware locations - i.e. not relative to the top of the OS). To implement this it proved necessary to use 8 separate 214-02 circuits to go down to the bottom TP bay. Each of these signals is inverted twice and then dot-ored with the inputs to the Next Three Byte select logic. These dot-or 's are only applied to the BYO , BYU , ... BY28 signals since using these, the proper h bytes will automatically be selected in each case. It should be noted that since the words in the OS are being chosen on "word boundaries", the special TP logic which inhibits OS writes past the OSTR position will not have any effect (see Section 2.3.1.3). The Pointer Register selection logic utilizes the same type of dot-oring technique except that its selection signals are dot-or'ed with the select signal outputs from the Name Register - Name Bus Compare logic. In the case of the Instruction Buffer Register selection the gating of the ICT to the IBR selection decoder must be inhibited by acti- vating IBRC/S. Then either the constant zero or four can be placed on the input to the decoder to fetch either the left or right half of the IBR, respectively. The Name Registers present a particular problem. They can be read out easily enough by using the logic which has been provided for use 1. The double inversion is necessary because 214-02 circuits may not be dot-or'ed. This implementation, however, is still faster than if some other circuit had been used to drive the cable to the bottom bay and had been dot-or'ed directly. 8/22/69 Section 4.7.3.2 - .3^ during interrupts. Unfortunately there is no direct way to load these registers. The only way is to indirectly load them by first loading the Shadow Name Registers (SNR's) and then gating the SNR's to the Name Registers. This would destroy the values in the SNR's however, and if the TP were in the middle of an imprimitive sequence name permutation this could be fatal. At the same time that the proper select signals are being activated, the control signals for reading or loading the registers are also turned on. In most cases this merely involves setting the proper read/write signals for the storage blocks or registers desired. In the case of a load operation it is also necessary to gate the data lines to the PRSNB bus and to gate this bus to the Permuter input. 8/22/69 Section 4.7.3-2 - h/h k.Q Turn-On and Initialization Turn-on and initialization consist of the processes involved in getting a TP without power into a state in which a task can he run on it. The purpose of this section is to describe, first in overall terms and then in detailed logic, exactly what must he done to accomplish this transformation. The turn-on' and initialization process can he broken down into four distinct phases: Power Turn-On, Register Clearing, TP Hardware Initialization, and TP System Initialization. Power Turn On consists of those operations which must be performed in order to successfully apply power to a Taxicrinic Processor. Register Clearing involves clearing all the TP registers as well as all the various flip-flops '?nd indicators. TP Hardware Initialization is the process whereby . registers are loaded with the information nec- essary for a TP to be able to run. TP System Initialization involves loading several system constants so that the TP can begin to execute the proper supervisor procedures to allow it to be assigned a task. 6/23/71 Section 1+.8 - l/l U 8.1 Power Turn-On Power turn-on consists of those operations which, must "be per- formed to successfully apply power to a Taxicrinic Processor and to set up the computer hardware for the TP Register Clearing stage. This latter process consists mainly of ensuring that all control points are in the cleared state. The major problem of power turn-on from the logical design point of view is to prevent the various random initial states of the machine when it is first turned on from initiating unintended operations in the logic. In order to do this the GOTASK and GODELY signals should both he forced to zero as soon as possible after the power is turned on. This will prevent sequences of unintended operations from propagating through the control logic. It will also prevent the task signals of all control points from turning on. Thus no control signals will be activated except for transient pulses directly due to the power turn-on itself. Once the power has settled down the GOTASK and GODELY signals may be turned on and a negative pulse can then be sent to the TP Hard- ware Initialization sequence to begin its operation. 6/23/71 Section U.8.1 - 1/1 k, 8. 2 , Register Clearing The Register Clearing phase of the TP Turn—on and Initialization process consists of ensuring that all control points are in the cleared state and that all registers and flip-flops are set to zero. The main operations consist of activating the common clear signal for all of the control points, generating a zero on the Distribution bus and loading all the registers with it, and clearing the flip-flops. In the case of clearing groups of registers such as the PR stor- age block it may be necessary to have a counter which is incremented and used to select each register in turn to be loaded with zero. 8/25/71 Section U.8.2 - 1/1 U.S. 3 TP Hardware Initialization The TP Hardware Initialization process is performed after all the control points have been reset. One of its primary purposes is to load the RP Name Registers with unique names ranging from to ill Another is to initialize the associative registers queue counters. In addition, certain other operations are performed. The PR Name Register initialization is performed by an initialize control sequence which makes use of the ACT and CCT counters, the Permute: and the IR arranged in the order shown in Figure h. 8.3/1. The ACT and CCT are initially set to zero and one respectively and then gated to the ■ positive constant generating signals of the Permuter. This causes the , low order byte output of the Permuter to contain the contents of the two j| counters. This output is then permuted and merged into the IR under , control of the middle two bits in the k bit ACT. , After one byte has been loaded, both counters are incremented by two and the process is repeated, this time loading the constants into a new byte. After h cycles, the IR will be loaded with 8 numbers, ; packed two to a byte, which is the same format used for storing the name registers during an interrupt. The interrupt return circuitry is then used to load these numbers into the first 8 name registers. The final 7 name registers are loaded by repealing the same process while the counters are counted the rest of the way to l6. 6/21/71 Section U.8.3 - 1/2 RMINES TATION MHIBITS NAME REGISTERS Figure 4.8.3/1 - Name Register Initialization 10/17/69 Section 4.8.3.1 - 2/2 U.8.U TF System Initialization Once the TP Hardware Initialization phase is completed, the TP must be loaded with enough information so that it can become activate, and successfully join the system. This is the job of the TP System Initialization phase. The main operations which must be performed are loading BR#0 with the base descriptor of the Supervisor task and then issuing the TP and Activate Interrupt (see Section 5-6. 5-2). Both of these operatic are performed by the Engineering Console, and therefore the details will not be described here. It is sufficient to say that the Engineerin Console is programmed so that it can start up a TP once it reaches the TP System Initialization phase simply by issuing the proper load commands and then giving the Exchange Net an ACTIVATE command with the proper initial address to cause the TP to begin the supervisor reactivation sequence. (This could also possibly be done by having the Engineering Console start up the TP Activate sequence directly). 9/26/69 Section U.8.U. - l/l k.A Control Point Logical Design Beginning with Section h of this manual, the largest part of the logical design consists of sequences of operations. Each control sequence in the Taxicrinic Processor has been broken down into control steps . These steps consist of task logic which performs the necessary operations by activating the proper control lines, and decision logic which determines which control step will be activated next. The control steps are performed by logical circuits called control points . Generally speaking each control step is performed by one control point. The purpose of this section is to explain the design and his- torical development of the control points used in the TP and to describe some of the more standard techniques which are used in the implementation of control sequences. In the following subsection, Section U.A.I, the historical development and final design of the elementary control point circuit is described. Section U.A.2 describes the design and use of the special calling control point while Section U.A.3 goes into the various design techniques used in implementing control sequences. 8/19/71 Section k.A - l/l k. A.1 Design of the Control Point The control point design for Illiac III has had a long and tor- tuous history. It originally developed as a modification of the Illiac II 12 3 "speed independent" control circuits.' ' The basic idea "behind a control point is that it initiates some operation by turning on a given set of control lines and leaves these control lines on until it either receives a reply indicating that the operation is over, or until a certain length of time passes . In general, a control point begins operation when it receives an advance in signal , A. . It then performs the operation it is designated to perform by activating a task signal , T, which in turn activates the necessary control lines. Finally, when the operation has been completed, • the advance out signal, A , is activated which in turn will activate the , U next control point. All of the control point designs which have been considered for the Illiac III system are centered about a flip-flop which determines the : state of the control point. However, the way in which this flip-flop is used has been subject to at least two different philosophical interpreta- tions. In the first interpretation the signal returning from the completed operation (or from the time delay model of the operation) is directly used to reset the flip-flop which in turn directly drives the advance out signal The advance out signal then remains on until the control point is reset. Examples of this type of use are shown in Figures U. 5.1/1 through U . 5 .1/^- (text continued on page 6) 1. Gilles, D.B., "A Flowchart Notation for the Description of a Speed Independent Control", Department of Computer Science File No. 386, August 196l. 2. Robertson, J.E., "Problems in the Physical Realization of Speed-Inde- pendent Control", Department of Computer Science File No. 387, August 196l. 3. Swartwout, R.E. , "One Method For Designing Speed- Independent Logic for a Control", Department of Computer Science File No. 388, August 1961. 7/10/69 Section kA .1 - l/7 orx ,,, ,,.. ..... „. oL 1 n-y- » 1 ^ -^r^ — — < i RESET - A 1 <3r ► A| ■ m t ►DO TASK This circuit, originally designed by K.C. Smith, contains a reset signal as well as a set signal. This allows the designer to develop logic sequences which skip certain operations simply by resetting the desired control points before entering the sequence. A possibly undesir- able feature of this circuit is that in order to maintain the outgoing advance signal, the incoming one must remain active. This means that, unless additional flip-flops are provided outside of the normal control point logic, the designer will run into a problem whenever any part of the sequence is turned off since this turnoff will propagate forward and eventually stop the operation of the control points. Figure U.A.l/l 7/10/69 Section kA.l - 2/7 SET * A, *A, ► DO TASK The above circuit was an attempt to control the "broken chain" effect mentioned in Figure U.A.i/i. in this circuit the control point flip-flop is directly used to generate the advance signal. Thus, once the control point task is completed the control point will continue to produce the advance signal until the control point is set for the next incoming signal. Note, however, that we have lost the ability to skip around control points by using a reset signal. This cannot be allowed in this circuit since a reset immediately triggers the advance signal to the next stage even independent of any input. Note also that in this circuit the number of logic elements has been reduced to 3 , 2 input NOR's and that both true and complement advance signals are available. Figure h .A. 1/2 7/10/69 Section U.A.1 - 3/7 SET • A >v nl^" ► "T> A Ar — > ^3 r> ♦~<> t> BAR/Q6 o DLR/G6 PRP/G6 Figure U.A.U/1 Example of Task Driver Logic 8/2U/T1 Section k.k.h - 3/5 "cable driven" line, i.e. it will have cable terminations at both ends. Note that the final stage is omitted for some signals. In these cases the output line will be going to some other set of task drivers and will be dot-ored at the second level in that set. The basic idea is to try to maintain an equal delay in all of the task driver paths. In Figure ^.A.U/l, these signals are represented as BAR/G2 and DLR/G5. The names on the task driver cards follow a simple convention, namely in all control signals with a slash and a final letter, a number indicating the drawing set is added at the end of the signal. If the control line does not have a /G, /W, or whatever, /Ei is arbitrarily added to the end where i is this same set number. The hardest part in designing the task signals is partitioning the output signals on the cards since in order to minimize the total numbei of pins used on all the task driver cards, it is necessary to place the drivers for control signals which are often turned on by the same control point task signals together on the same card. This minimizes the number o; j cases where a single task signal from a control point has to get to many , different task driver cards. Unfortunately the partitioning job can be extremely time consuming. As a result the general tendancy has been to do a quick and dirty partitioning based on an a priori knowledge of which of the most common control signals get turned on together and then putting the less commonly used signals in whatever spaces seem most convenient. This is the result of the realization that the cost inherent in, say, usin one more card than necessary in a non-minimal design will be a lot less than the cost in time of trying to get a minimum partitioning, expecially since the task driver logic has a very high probability of being changed due to additions or deletions in the logic. The general partitioning method is based on the use of a table which lists all of the signals (in alphabetical order) along one border and all the task and conditional task signals (in numerical order) along the other border. Check marks are then made along each column to indicate if a given task signal must turn on a given control signal. From this table it is possible (with varying amounts of effort) to decide how to group the control signals so that each task signal will have to go to a minimum number of task driver cards. The final step in the control sequence design process is to update the original control step flow chart so that it reflects the final logical design. This is helpful as a final check and it also produces a document which can be used as a reference in checking out the logical design at a later stage. In particular each box in the control step flow chart should be labelled with the name of the task signal or conditional task signal which it represents. If it represents more than one signal, the respective names should be grouped together and separated from the other groups by dotted lines and each group should be separately labelled. In its general layout, the control step flow chart should follow the logical design, i.e. the parts of the flow chart corresponding to each logic card should be delimited by dotted lines across the entire flow chart. Lines crossing these delimited areas as well as those coming from entry and exit circles represent specific control lines on the logic cards and should be so labelled. This allows for easy comparison between flow chart and logic. 8 / 1 9/Tl Section k.A.k - 5/5 rmAEC-427 U.S. ATOMIC ENERGY COMMISSION SfSoi UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFC AND TECHNICAL DOCUMENT ( See Instructions an Reverse Side ) AEC REPORT NO. C00-2118-0022 2. TITLE Illiac III Computer System Manual; Taxicrinic Processor, Vol. 2 i TYPE OF DOCUMENT (Check one): [3 a. Scientific and technical report L] b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference Sponsoring organization []c. Other (Specify) _^ 1. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): 1-^1 a. AEC's normal announcement and distribution procedures may be followed. J b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. 1~1 c. Make no announcement or distribution. \. REASON FOR RECOMMENDED RESTRICTIONS: SUBMITTED BY: NAME AND POSITION (Please print or type) Bernard J. Nordmann, Jr. Research Assistant Organization Department of Computer Science University of Illinois Urbana, Illinois 6l801 Signature ^ - A Date August 30, 1971 FOR AEC USE ONLY AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: PATENT CLEARANCE: LJ a. AEC patent clearance has been granted by responsible AEC patent group. U b. Report has been sent to responsible AEC patent group for clearance. U c. Patent clearance not required. **