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LIBRARY OF THE 
 
 UNIVERSITY OF ILLINOIS 
 
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 no. 188-199 
 
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Report No. 188 
 »ft.lt? 
 
 
 u? 
 
 HYBRID CIRCUITS FOR THE PARAMATRIX SYSTEM 
 
 by 
 Edward F. Prozeller 
 
 September 7, 19^5 
 
 j ii 
 
 DEC y MS5 
 
Report No. 188 
 
 HYBRID CIRCUITS FOR THE PARAMATRIX SYSTEM 
 
 by 
 Edward F. Prozeller 
 
 
 September 7, 1965 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 
 
Sio. f H 
 
 ACKNOWLEDGEMENT 
 
 CjJ 
 
 The author wishes to express his sincere thanks to his advisor, 
 Professor W. J. Poppelbaum, for his excellent counsel, support and 
 encouragement . 
 
 The author is also indebted to his colleague Michael Faiman 
 for his friendship, encouragement, and many ideas resulting from discussions 
 of the topics contained in this thesis. 
 
 Thanks are also extended to Mrs. Frieda Anderson and Miss Bonnie 
 Malcor for typing the manuscript. 
 
 
 11 
 
Y4 ■'.<'■'-'• 
 
 TABLE OF CONTENTS 
 
 Page 
 
 1. INTRODUCTION 1 
 
 2. DIAMOND GATE 3 
 
 2.1 Circuit Requirements and Possible Solution 3 
 
 2.2 Circuit Analysis 5 
 
 2.3 The Method of Constant-Current Bias 6 
 
 2.U The Method of Bypass-Gating 11 
 
 2.5 Diamond Gate for Paramatrix 11 
 
 2.6 Diamond Gate with Gain 15 
 
 3. ANALOG COMPARATOR l8 
 
 3.1 Differential Input Stage 18 
 
 3.2 Linear Analysis of the Differential Stage 20 
 
 3.3 Sensitivity Selection and Practical Design 
 Considerations 23 
 
 J>.\ Specific Requirements 26 
 
 3.5 Analog Comparator for Paramatrix 27 
 
 k. APPLICATIONS OF HYBRID CIRCUITS 31 
 
 k.l Circuit Requirements and Notation 31 
 
 k.2 Paramatrix Digital-to-Analog Conversion 31 
 
 U.3 Paramatrix Function Generation and Interpolation 35 
 
 5. SUMMARY AND CONCLUSIONS 39 
 
 REFERENCES i+2 
 
 APPENDIX A. . U3 
 
 APPENDIX B. . . U5 
 
 in 
 
1. INTRODUCTION 
 
 Currently under development in the Task 15 Group of the Digital 
 Computer Laboratory is a pattern processing system called Paramatrix. The 
 inputs to Paramatrix consist of line drawings which have been encoded into 
 a discrete set of 32 d-c voltages lying in the interval +8 to -8 volts. The 
 output of the system consists of the visual presentation of the input pattern, 
 renormalized in position, size and azimuth. Hence, apart from input-output, 
 the purpose of Paramatrix is to sequentially translate, rotate, and/or 
 magnify a bounded set of analog voltages. The transformed analog data are 
 then digitized in order that they can be used by a digital computer or, as 
 in the present system, to drive a matrix of flipflop circuits for the purpose 
 of visual display. 
 
 Obviously the above operations can be performed by a digital 
 computer provided the input patterns have been digitized. Equally apparent 
 however is the ease with which the above transformations can be achieved using 
 high-speed analog techniques, namely, rotation from a sine-cosine potentio- 
 meter, magnification from an ultra-linear d-c amplifier and finally translation 
 by means of d-c level shifting. In the Paramatrix system we have attempted 
 to combine the advantages of both analog and digital, techniques. The result 
 is a special-purpose analog-digital computer in which the information signals 
 are analog and the control signals are digital. 
 
 In order to realize the Paramatrix system it was necessary to 
 design three types of circuitry. First the system required conventional 
 digital circuits for timing and scanning. The second requirement was for 
 for ultra-compensated analog circuits capable of handling the system 
 information with great precision (negligible loss) and at a fast sampling 
 rate (100 KC or better). Finally, the requirements called for rather elegant 
 
 •1- 
 
-2- 
 
 analog-digital (hybrid) circuits in order to achieve digital-to-analog 
 conversion and analog comparison. 
 
 The purpose of this thesis is to describe in detail the design of 
 two hybrid circuits, namely, an analog gate and an analog comparator. In 
 addition the design of a precision analog circuit, namely, a compensated 
 emitter-follower, will also be discussed. Finally, a brief description will 
 be given of the applications of these three circuits in a hybrid system 
 like Paramatrix. 
 
2, DIAMOND GATE 
 
 2.1 Circuit Requirements and Possible Solution 
 
 The first hybrid circuit required by the Paramatrix system was an 
 analog gate. This is essentially a switch which is shorted when a digital 
 signal is applied and open at all other times. 
 
 It was required that the switch be more ideal than the conventional 
 transistor model since an absolute offset greater than 80 mv could not be 
 tolerated. In addition it was necessary to gate voltages over the unusually 
 wide range of -8 to +8 volts . 
 
 A circuit which is often used for voltage gating in analog computers 
 
 is shown in Figure 1. In this circuit the bridge is biased on from t to t 
 
 and if v = and the diodes are matched, it is reasonable to assume 
 s 
 
 + E-- 
 
 *-0 v 
 
 > R L 
 
 _E 
 
 
 Figure 1. Conventional Analog Gate 
 
-h- 
 
 that the current through each diode is 
 
 'DQ "' 2R 
 
 (2.1) 
 
 If the usual diode curve of Figure 2(a) is assumed for each bridge diode and 
 
 an offset AV = v - v is defined, then visibly AV = for the quiescent 
 so 
 
 condition v =0. Figure 2(b) shows the changes in the diode currents when 
 a positive input signal is applied. In this case a voltage offset is 
 encountered since D now conducts less current and D more. However, the 
 offset is substantially less than the drop across a single diode because of 
 the complimentary connection . 
 
 V DQ v 
 
 QUIESCENT CONDITION 
 
 (a) 
 
 V D 1 V D 3 
 SIGNAL APPLIED 
 
 (b) 
 
 v o 
 
 Figure 2. Diode Curves 
 
 The main consideration in the design of a precision analog gate 
 to minimize the offset AV. In the diamond gate of Figure 1 minimum AV is 
 
 r\\T 
 
 eved when I„. is maximum since in this case — is minimum. To achieve a 
 1H dl 
 
 large I either E must be made large and/or R small. 
 
-5- 
 
 2„2 Circuit Analysis 
 
 A simplified analysis can be made of the diamond circuit if it is 
 assumed that all diodes conduct with negligible forward resistance and we 
 neglect any source impedance. In this case the absolute maximum value of 
 
 v as a function of E can be calculated such that all the bridge diodes 
 
 F 
 conduct. As before, the quiescent diode current equals — and if all diodes 
 
 are to conduct^ the signal current i through the input diode D (for 
 
 S _L 
 
 positive input) must not exceed I-p^. An a-c equivalent circuit for Figure 1 
 
 is given in Figure 3. From this model the signal current i is found to be 
 
 s 
 
 1 = 
 s 
 
 v (2R T + R) 
 
 s " L 
 
 2RR T 
 
 (2.2) 
 
 VgO 
 
 Figure 3„ A-C Equivalent Circuit for Analog Gate, 
 
 The condition for the bridge to be biased on then becomes from Eq. (2.2) 
 and L s < J DQ 
 
 V S < 2R L + R) E 
 2RR T * 2R 
 
 (2.3) 
 
-6- 
 For a symmetrical signal swing about ground it is easy to see bl 
 condition (2.3) becomes 
 
 ER 
 
 2R T + R 
 
 Li 
 
 (2.10 
 
 Equation (2ji) merely g.ives the condition that all diodes conduct; however, 
 for low offset it is required that all diodes conduct well above the knee on 
 the characteristic curve. It is reasonable therefore to state t 
 condition for low offset as 
 
 1 ER L 
 l v s l <k ( 2lTTlr 
 
 If in the above equation. R » R, then 
 
 v B | <g(E) 
 
 (2.5) 
 
 and if |v | = 8 v (as required), E > 6h v. Two bias supplies of this size is 
 quite unreasonable, especially since, in order to switch the circuit, these 
 biases must be switched. 
 
 2.3 The Method of Constant-Current Bias 
 
 Because of the unusually large signal swings required it became 
 necessary to invent a more elegant method of biasing the diamond. It is 
 logical that if a large quiescent current is maintained in the diodes 
 independent of signal current then a constant-current bias will give a 
 satisfactory solution. 
 
-7- 
 
 Assuming a constant-current bias I_ and an exponential v-i 
 
 characteristic for the bridge diodes^ it is possible to derive an equation 
 
 for the bridge offset, AV, as a function of I_ and i . Consider the circuit 
 ° ' ' s 
 
 of Figure h. Under the above assumption each of the diodes obey the equation 
 
 qV./KT 
 
 (2.6) 
 
 or 
 
 v - r m (i + f 
 
 (2.7) 
 
 sj 
 
 INO 
 
 O OUT 
 
 Figure U„ Analog Gate with Constant -Current Bias. 
 
where in the above : 
 
 I = current through jth diode 
 
 J 
 
 V. = voltage drop of jth diode 
 
 J 
 
 I = saturation current for jth diode 
 
 K = Boltzman's constant 
 
 T - temperature (assume constant and equal for all diodes) 
 
 q_ = magnitude of electronic charge 
 
 Writing I n = i, it follows that I_ = i + i, I_ = I. - i and I, = I. - i - i, 
 D 1 ' 2 s ' 3 M- s ' 
 
 as shown. The condition that V + V = V + V, gives , from (2.7) 
 
 i i+i I - i I n - i - i 
 
 (i + — )d + -? — ) = (i + -V-)d + -^ — ) 
 
 (2.8) 
 
 "si 
 
 "s2 
 
 "s3 
 
 ->k 
 
 It is most instructive to consider the solution of Eq. (2.8) when all diodes 
 
 are identical, i.e., when I . =I_=I_=I,. The quadratic term in (2.8) 
 
 ' ' si s2 S3 S4 
 
 then drops out and the unique solution is 
 
 1 - 5 fro - V 
 
 (2.9) 
 
 Thus 
 
 h-h 
 
 K 
 
 i s ) and I 2 = I 3 = | (i s + I Q ) 
 
 (2.10) 
 
 It is also interesting to note that if each diode is assumed to have 
 a small series ohmic resistance r, Eq. (2.7) would be replaced by 
 
 KT I. 
 
 V. = — In (l + =J-) + rl. 
 
 (2.11) 
 
 The solutions (2.10) still hold for identical diodes; however Eq. (2.1l) is 
 probably a more realistic equation for a real diode. 
 
■9- 
 
 We are mainly interested in the voltage offset AV which 
 
 becomes 
 
 AV = V 3 - V x = V^ - V 2 
 
 (2.12) 
 
 It is convenient to make two approximations: 
 
 (a) that I_ - li I » I , which is almost certain to be true if 
 
 ' s ' s 
 
 all diodes are forward biased; 
 
 (b) that i « I , which may or may not be true. 
 Then from (2.1l), (2.12) and (a) 
 
 KT I _>■+ i 
 
 AT7 -, s 
 
 AV = — In : — f r i 
 
 * J ~ X s 
 
 (2.13) 
 
 If (b) is also true, (2.13) can be simplified still further since, 
 
 I. + i 2i 2i 
 
 In {- — 7-7-) - In (1 + —J - - — 
 
 s " s 
 
 (2.14) 
 
 Thus Eq. (2.13) becomes 
 
 AV - (^ + r ) i 
 •ql 
 
 It is useful to define a figure of merit for the circuit with 
 constant -current bias, namely 
 
 AV „ 2KT , . 
 
 R„ * ■ — — — -— + r = constant 
 
 ° X s *0 
 
 (2.15) 
 
 (2.16) 
 
 It will be noted that this figure of merit is in ohms and is equal to the 
 magnitude of offset voltage divided by the load current (load current equals 
 
-10- 
 signal current when constant -current bias is used). Obviously, the lower the 
 figure of merit, the better the circuit. 
 
 The realization of a diamond gate with constant-current bias is 
 actually quite straightforward. A realizable topology is shown in Figure 5. 
 
 v« O 
 
 O + B 
 
 Ov f 
 
 O-B 
 
 Figure 5. Diamond Gate with Current Generators. 
 
 E-B 
 
 In this circuit the bias current I is approximately equal to 
 
 (J K 
 
 and the 
 
 collectors of the driver transistors can swing about + B volts before an 
 
 intolerable change occurs in 1^. Hence the requirement on v has now been 
 
 s 
 
 reduced to |v | < B which is easier to achieve than the conditions given by 
 (2.5). 
 
-11- 
 
 2 A The Method of Bypass -Gating 
 
 In order to switch the circuit of Figure 5 most efficiently (i.e., 
 no power is dissipated when the bridge is off) it is necessary to cut off 
 the transistors by applying voltage pulses of magnitude +C and -C (where 
 |CJ > E) to the bases of T and T respectively, This is undesirable because 
 it would require a power supply greater than E which is already large due to 
 the offset requirements of the diamond . 
 
 An alternate method of switching the diamond, called Bypass-Gating, 
 is shown in Figure 6„ When transistor T is on, T and T are held off and 
 I flows through T instead of the bridge and the output v essentially 
 floats. When T is off the bridge is biased and 
 
 v_ = v + AV 
 s 
 
 The resistors R , R serve to bias the zener which shifts the gate voltage 
 
 to a level sufficient to control transistor T 
 
 3 
 
 2.5 Diamond Gate for Paramatrix 
 
 The final diamond gate designed for the Paramatrix system is of 
 the above type and is shown in Figure 7° The quiescent bridge current, I , 
 is 15 ma and the results of a static test of this circuit are given in 
 Table 1 and plotted in Figure 8.* The figure of merit, R , for this design 
 
 * A quiescent offset AV exists because the bridge diodes are not 
 perfectly matched. 
 
-12- 
 
 + EO • 
 
 GATEO 
 
 O + B 
 
 O-B 
 
 Figure 6. Bypass -Gating of Current— Driven Diamond. 
 
-13- 
 
 mztfi 
 
 
 +25v 
 
 (S)iN964 
 
 >68K=r 
 
 GATE 
 
 -25v 
 
 Figure 7„ Diamond Gate for Paramatrix, 
 
-lu- 
 
 ll 
 
 < 
 O 
 
 -I 
 
 > 
 
 < 
 
 UJ 
 
 </> 
 
 Ll 
 
 o 
 > 
 
 E 
 
 CO 
 t> 
 
 o 
 ft 
 
 CO 
 
 00 
 
 CD 
 •H 
 
IS 
 
 -15- 
 
 R, 
 
 Ai 
 
 
 
 76 
 
 8,2 ft 
 
 i ( ma ) 
 
 1 
 
 2 
 
 3 
 
 1+ 
 
 5 
 
 6 
 
 7 
 
 8 
 
 9 
 
 AV (mv) 
 
 5 15 
 
 22 
 
 '41 
 
 ^0 
 
 ^8 
 
 56 
 
 65 
 
 7U 
 
 81 
 
 Table 1, Static Test Data for 1 = 15 ma, 
 
 KT 
 It is interesting to note that if we use Eq„ (2„l6) with r = 0, and — = r-r, 
 
 then the ideal figure of merit for I = 15 ma is R^ = 6 ft which, considering 
 
 the approximations involved in the derivation, is a fairly good comparison. 
 
 The dynamic performance of the diamond is quite good. The rise time 
 
 of the circuit is mainly a function of the bridge resistance and the junction 
 
 capacitances of the bridge diodes and T and T_. Since the bridge resistance 
 
 is very small the rise times are quite fast, typically on the order of ^0 ns . 
 
 The fall times however are a function of the junction capacitance and the 
 
 output resistance of the bridge which is usually 1 to 2 K As a result the 
 
 fall times are slower, typically 100 ns for a 1 K load. The addition of 
 
 resistors, r, to the circuit have the effect of back-biasing the bridge when 
 
 the bias current is removed and results in a faster fall time. 
 
 2 „ 6 Diamond Gate w ith Gain 
 
 One last point should be brought out concerning the diamond gate 
 as discussed in this chapter, namely, that it is a completely passive element 
 All of the current that is required by the load must be supplied at the input 
 of the circuit. 
 
-16- 
 
 Obviously it would be very desirable to have a gate which is 
 
 capable of providing current gain. Some effort has been made to design such 
 
 a circuit and the results have been favorable. The circuit of interest is 
 shown in Figure 9. 
 
 v« 0-H> 
 
 X s 15ma 
 
 6 -° 
 
 Figure 9. Transistorized Diamond . 
 
 The purpose of the small resistors, r } is to balance the right 
 
 and left sides of the bridge in order that the bias current I will split 
 
 evenly when the input is at ground. This is necessary since the junction 
 
 drop of the diodes is greater than the emitter-base drop of the transistors 
 
 at 7.5 ma. The maximum offset observed in this transistor circuit is 180 mv 
 
 at i_ = 8 ma. Though this offset seems high it is quite easily explained by 
 
 considering the current change in resistor r. When v = we have 7.5 ma 
 
 s 
 
-17- 
 
 through T and when v = +8 v (i = 8 ma) we have (from Eq„ 2„9) 
 
 _L s 1j 
 
 approximately 3»5 ma through T and since r is a linear element, 
 the total voltage change across r alone is 80 mv„ 
 
 Thus it can be seen that if r could be eliminated by obtaining 
 transistors and diodes with matched junction drops at quiescent current, an 
 offset of 100 mv or lower could be easily achieved „ In this case the circuit 
 of Figure 9 with its property of current gain would be very useful „ 
 
3. ANALOG COMPARATOR 
 
 The Paramatrix system required the design of an analog 
 comparator circuit with two rather special characteristics. First, it was 
 necessary to compare analog voltages over the unusually wide range of +8 to 
 -8 volts and furthermore it was required that the sensitivity of the voltage 
 comparison be adjustable over the range 0.2 to 2.0 volts. It was also 
 desired that this sensitivity adjustment be voltage-controlled. 
 
 3.1 Differential Input Stage 
 
 The input stage for a comparator often consists of the differential 
 
 [2] 
 connection shown in Figure 10. It has been shown in the literature that 
 
 if the input pair is driven by a constant -current source, the switching 
 
 sensitivity is very high. In fact, if the emitter resistors, r, are set 
 
 w 2 o 
 
 Figure 10. Comparator Input Stage 
 
 -18- 
 
•19- 
 
 equal to zero, then as small as a 0.1 v difference in inputs will switch about 
 90 per cent of the standing current I through one transistor. If r is 
 increased in both emitters equally., a larger voltage difference is required 
 to achieve the same result. This phenomenon is shown graphically in 
 Figure 11. It is sufficient to consider only the emitter-base junction 
 
 characteristics since v 
 
 v = v - v 
 1 2 1 ' eb eb 2 
 
 for the case r = 0. For the 
 
 case r ^ 0^ one can obviously form a combined characteristic of the junctions 
 in series with the resistance r (as shown). 
 
 U»0 
 
 note : 
 
 Figure 11. Graphical Analysis of Input Stage, 
 
-20- 
 
 3„2 Linear Analysis of the Differential Stage 
 
 If we assume transistors T and T to be identical, d-c Ot's 
 and neglect the emitter-base drops with respect to ir, then a linear 
 analysis can be made of the differential stage. From consideration of 
 Figure 10, it is clear that 
 
 = 1, 
 
 < v i 2 < i 
 
 (3.1) 
 
 Hence letting v = v + £ and v = v, we have 
 
 v + e - i n r = v + i n r - I r 
 1 1 o 
 
 and from symmetry 
 
 I o r + e 
 X l ~~ 2r 
 
 (3.2) 
 
 X 2 " 2r 
 
 (3.3) 
 
 Due to restrictions (3.1)., the detectable input differences lie in the 
 range, 
 
 V < € < I r 
 
 (3 JO 
 
 that is, the circuit saturates for all |e| > I n r . From Eqs . (3.2) and (3.3) 
 the collector voltages become 
 
-21- 
 
 w. 
 
 Wg = € 
 
 R 
 
 2r •' 
 
 R 
 
 <5> 
 
 RI 
 
 + E 
 
 (3.5) 
 
 RI, 
 
 4 E 
 
 It is instructive to consider Eqs „ (3.5) and restriction (3.*0 graphically, 
 as shown in Figure 12 „ Due to the symmetry of these curves, it is 
 
 W1.W2 
 
 Tl OFF 
 
 SLOPE = ^r 
 
 Figure 12, 
 
 T2 OFF 
 
 SLOPE = -77T 
 
 R_ 
 2r 
 
 Graph of w , w vs e 
 
 obviously not necessary to look at both collectors to determine 
 coincidence or noncoincidence of the input signals. Clearly, it is 
 sufficient to look at only the smaller of the collector voltages (i.e., 
 min (w , w )) as shown by the darkened portion of the curves . Let us 
 
 define 
 
-22- 
 
 and 
 
 w = min (w , w ) 
 
 T] = |e 
 
 (3.6) 
 
 Hence the graph of Figure 12 can be simplified to that shown in Figure 13. 
 
 f COINCIDENCE 
 
 jl NON-COINCIDENCE 
 
 E-RX -- 
 
 I*r 
 
 Figure 13* Simplified Graph, 
 
 It is useful at this point to assume a threshold voltage V* (which 
 is in the range of w) and to define what we mean by coincidence and non- 
 coincidence of input signals in terms of this voltage. The following are 
 reasonable definitions 
 
 w > V* means coincidence of input signals 
 
 w < V* means noncoincidence 
 
 (3.7) 
 
 If V* = E - RI n /2 there is clearly only one point of coincidence, viz., 
 = 0. However, if V* < E - RI /2, as illustrated in Figure 13, it is 
 
-23- 
 possible to have coincidence for all t\ < r\ ' . This latter point illustrates 
 one method of achieving sensitivity control, i.e., adjustment of the 
 threshold voltage. 
 
 3„3 Sensitivity Selection and Practical Design Considerations 
 
 In order to convert the differential amplifier to an analog 
 comparator it has been pointed out that two modifications are necessary. 
 First, a circuit is required which will respond only to the lowest of the 
 collector voltages and second, some method is required to adjust the 
 comparator sensitivity. While it has been shown that sensitivity selection 
 can be achieved by varying the threshold voltage, V*, it is desirable from the 
 standpoint of circuit efficiency to adjust sensitivity by varying w (Figure 13) 
 with V* fixed throughout the sensitivity range. 
 
 A very elegant, yet simple circuit which will serve both of the 
 above functions is the diode "or" circuit. The cathodes are connected to 
 the collectors of the input transistors and the anodes are fed through a 
 resistance to a variable supply, S. Varying S over the range 
 
 V* < S < E 
 
 (3.8) 
 
 will result in the variation of r\ ' over the range 
 
 < V < v 
 
 (3.9) 
 
 In order to derive the final circuit equations we will analyze 
 the circuit of Figure 14, again assuming ideal transistors and diodes. 
 The analysis becomes somewhat simpler if we define the emitter currents as 
 
 ■i = l (l o + i} 
 
-2k- 
 
 i„ = 
 
 1^0 
 
 and hence, g = ri. 
 
 v+€0 
 
 O v 
 
 Figure Ik. Modified Differential Amplifier. 
 
 Nov with £ > we assumed D. on and D off, so that 
 
 w . w 1 < w 2 
 
 Tnen, writing KCL equations at w , we have 
 
 | <I + i) - | d + 6 /r) 
 
 E - w S - w 
 ~~R + ~~R 
 
■25- 
 
 or 
 
 v 1 = w = | (E + S) - j^RfI + g/r) 
 
 (3.10) 
 
 Thus if it were true that only one diode were on,, w as a function of r\ = |ej 
 and S would appear as shown in Figure 1'3 * (This should be compared to Figure 
 13.) The sensitivity selection property of the modified circuit is obvious. 
 Of course it is not always true that only one diode is on at a time; with 
 r\ = both diodes are on. Then w = w , • say,, which is given by 
 
 2E + S - 3w 
 
 T 
 
 
 
 or 
 
 w_ = 7 (2E + S - R] 
 
 (3-11) 
 
 w 4 
 
 V=Vi 
 
 ^v s v^ 
 
 Inf 
 
 S = S 3 
 S = S 2 
 
 Figure 15 . Modified Differential Amplifier Response 
 
-26- 
 Depending on the magnitude of S, w can be either greater or less than the 
 limit of w as £ -» in Eq. (3.10). Furthermore, let us calculate w on the 
 assumption that D is off: 
 
 1 l E - w 
 
 \ <l - i) - \ (l - e/r) - -^ 
 
 or 
 
 w. 
 
 = E - |R(I - e / r ) 
 
 Then 
 
 w. 
 
 Wi = |( E .S)-iR(l -^) 
 
 (3.12) 
 
 which shows that, if e < — r I and (E - S) is small enough, it is not 
 necessarily true that w > w . In this case we have w = w = w , even 
 though t\ ^ 0. 
 
 3.^ Specific Requirements 
 
 As previously discussed, we must now choose some threshold voltage 
 
 V* from the range of possible values of w and make the definitions as given 
 
 in Eq. (3.7). Then varying S alters the value of t) 1 (recall that for all 
 
 r\ < t]' the inputs are the same) and hence provides our sensitivity 
 
 selection. 
 
 It is convenient to set S = E and S . = V*. We also require 
 
 max mm 
 
 that, for S = E and g = rl , w = V*. Hence from Eq. (3.10) 
 
 V* = I (E + E) - |r(I + I Q ) 
 
 or 
 
■27- 
 
 RI = 2(E - V*) 
 
 (3.13) 
 
 We notice that, for S = V* and RI given by (3.13), Eq. (3.1l) gives 
 
 w = - (2E + w - 2E + 2w) = 
 
 w 
 
 which is due to choosing the sensitivity resistor equal to the collector 
 resistors. 
 
 Finally substitution of Eq. (3.13) in Eq. (3. 12) gives 
 
 w 2 - W l = { B e " 2 (S " W) 
 
 Hence the on-off diode condition is satisfied if 
 
 2r 
 3R 
 
 T] > — (S - V*) 
 
 (3.1*0 
 
 3»5 Analog Comparator for Paramatrix 
 
 The comparator circuit which was designed for the Paramatrix 
 
 system is shown in Figure l6. For this circuit the emitter of T is tied 
 
 to the threshold voltage V* = 10 v and the digital output signal is taken 
 
 off the collector of T, . Hence for coincidence w > 10 v and v = v; 
 
 k o 
 
 for noncoincidence w < 10 v and v = -5 v. We also have from Eq. (3.1l) 
 
 o 
 
 » - 5 (20 + S) 
 
 if both diodes are on. From Eq. (3.10) for only one diode on we have 
 
 w = 5 + I S - 3.T5T] 
 
 (3.15) 
 
•28- 
 
 +*t* 
 
 i*3K 
 
 4 
 
 /\ 
 
 3.*K Dl 
 
 14- 
 
 D2 
 
 - 14 
 
 22on 220a 
 v> 
 
 O IN ? 
 
 I, 
 
 3K 
 
 -*5v 
 
 Tl, T2 : SM5306 
 TS.T4: SM1290 
 Di, D2: S-3506 
 
 10K > T4 
 
 OUT«v, 
 
 Figure l6. Paramatrix Comparator 
 
 and finally for (3.15) to be true we require that 
 
 t, > Sf (s - io) 
 
 (3.16) 
 
 These results are illustrated graphically in Figure 17. It will be 
 noticed that the case of both diodes conducting (w = w ) for noncoincident 
 input signals occurs only at S = 10 v, i.e., -q' =0. 
 
 Naturally the foregoing analysis of the comparator circuit has 
 been an ideal one. In the real world the curves of Figure 17 would be 
 
 'ferent since transistors do not have infinite P's, junction drops are not 
 
^m 
 
 -29- 
 
 £ 
 
 > > > > > 
 
 ^- ro cvi — o 
 
 > 
 
 CO 
 
 o 
 
 •H 
 -P 
 
 w 
 
 •H 
 ?H 
 
 -p 
 
 CJ 
 
 co 
 
 Jh 
 CO 
 
 o 
 
 o 
 •p 
 
 CD 
 U 
 CO 
 
 & 
 
 o 
 o 
 
 H 
 
 CO 
 CD 
 
 -a 
 
 c- 
 
 •H 
 
-30- 
 zero and thresholds cannot be defined exactly. However these effects can 
 be somewhat reduced when necessary by using higher currents and voltages. 
 
 The circuit of Figure l6 approaches quite closely the 
 characteristics of Figure 17 except at the extremes of the sensitivity 
 voltage S where we would expect the real curves to be quite rounded. The 
 experimental sensitivity data for the Paramatrix comparator is given in 
 Table 2. 
 
 s 
 
 V 
 
 10 v 
 
 No coincidence 
 
 12 v 
 
 0.2 v 
 
 13 v 
 
 0.38 v 
 
 16 v 
 
 0.78 v 
 
 19 v 
 
 1,25 v 
 
 22 v 
 
 I065 V 
 
 2k v 
 
 2,0 v 
 
 25 v 
 
 No noncoincidence 
 
 Table 2. Experimental Data 
 
 for Paramatrix Comparator, 
 
k. APPLICATIONS OF HYBRID CIRCUITS 
 
 k„l Circuit Requirements and Notation 
 
 The applications suggested by W. J. Poppelbaum, which we are 
 about to discuss, will require the use of the analog comparator, the 
 diamond gate, and a low-offset current amplifier which we will call a 
 compensated emitter-follower. This latter device has been designed for the 
 Paramatrix system and is described in Appendix A. When a compensated 
 emitter -follower is used at the input of a diamond gate the resulting 
 device is a diamond gate with current gain (essentially equivalent to the 
 circuit of Figure 9). Clearly, in this case, the requirement that the 
 diamond be driven from a low-impedance source is substantially relaxed. 
 
 The basic block diagrams which will be used in the following 
 discussions are shown in Figure 18. 
 
 k.2 Paramatrix Digital-to-Analog Conversion 
 
 The term digital-to-analog conversion normally means that one 
 digital pulse is considered equivalent to a preset d-c voltage V . A 
 chain of n digital pulses at the input of a digital-to- analog converter 
 will result in a d-c output of nV^ independent of the time at which the 
 pulses occur. 
 
 In the Paramatrix system the term digital-to-analog conversion 
 carries a slightly different connotation, namely that one digital pulse 
 depending on where it occurs in time (relative to the system clock) will 
 produce one predetermined analog level during the duration of the pulse . 
 Possibly a more descriptive name for this would be digital-to-sampled- 
 analog conversion. The basic layout of the Paramatrix digital-to-analog 
 converter is shown in Figure 19 together with the output waveshapes which 
 
 -31- 
 
-32- 
 
 when G = 1. v W v 
 ' 2~1 
 
 when G = 0, v floats 
 
 (a) Diamond Gate 
 
 when | v. - v | < T) ' , G = 1 
 when \v - v | > T) ' , G =» 
 T]'(s) = comparator sensitivity 
 as a function of sensitivity 
 voltage (as in Figure l6) 
 
 (b) Analog Comparator 
 
 v iO 
 
 c> 
 
 f Y : 
 
 v = v 
 2 1 
 
 i -•- Si 
 2 - p 1 
 
 (c) Compensated Emitter -Follower 
 
 ' v. 
 
 when G = 1, v ~v 
 when G = 0, v floats 
 
 (d) Diamond Gate with Current Gain 
 
 Figure 18. Circuit Notations. 
 
'S/s'-'.'Wj 
 
 Wy* 
 
 
 31 
 
 n-TLTLTL. clock 
 
 I I 
 
 i i i 
 I ! ! 
 
 n 
 
 i i 
 
 x - 
 
 n 
 
 n 
 
 t~ gx 
 
 i 
 
 f- gXi 
 
 -- <jx 2 
 
 OUTPUT 
 
 ov 
 
 t 
 
 OUTPUT 
 
 Figure 19. Paramatrlx D/A Converter and Waveshapes 
 
-3^- 
 are produced. The gating signals gX. are decoded clock times and since 
 they do not overlap, only one analog voltage exists on the output bus at a 
 time. 
 
 As was described in the introduction to this thesis, the output 
 of the Paramatrix system is displayed on a 32 x 32 matrix which is scanned 
 by the system clock. Thus to each coordinate corresponds two digital signals 
 gX., gY. and, by means of the digital-to-analog converter of Figure 19, each 
 matrix coordinate also corresponds to a set of analog levels X., Y.. These 
 analog voltages are the signals which serve as the inputs to the transformation 
 circuitry. An illustration of this is given in Figure 20. 
 
 ysr 
 
 V2 
 
 
 *0 x i*2 
 
 / 
 
 (gX 31 ,gY 2 ) 
 $- (X 31 ,Y 2 ) 
 
 X 
 
 31 
 
 Figure 20. Matrix -Coordinate Representations. 
 
-35- 
 
 k.3 Paramatrix Function Generation and Interpolation 
 
 The input information to Paramatrix consists of voltage levels 
 in the range -8 to 8 volts which have been set on potentiometers, one 
 potentiometer for each of the 32 columns of the matrix. Hence at each 
 column x. we have potentiometer voltage setting F(x.)„ As discussed in 
 Section U.2, to any coordinate x. there corresponds a reference voltage 
 X. and hence the equivalence of 32 x columns to 32 quantized reference 
 voltages is apparent. 
 
 A simple look-up system by which one can find F(x. ) provided 
 its x coordinate is known through its voltage analog X., is shown in 
 Figure 21. In this device if X* is an exact x coordinate (say X* = X.), 
 it will compare with only one quantized reference level, namely X., 
 provided 
 
 (x )O 
 
 O F(x ± ) 
 
 F(x L ) 
 
 F(x 3 , )Q 
 
 OUTPUT BUS 
 
 V 
 
 ri 
 
 > 
 
 F(x L ) 
 
 Figure 21. Look-up System. 
 
-36- 
 
 tT(s) <| |x. 
 
 X 
 
 i-1 1 
 
 t 
 
 When the comparison is made, comparator i will give a "l" output signal 
 which will gate the potentiometer set to F(x. ) onto the output bus. The 
 potentiometer settings in the above essentially constitute the input 
 program. 
 
 The above discussion applies only in the case when the Paramatrix 
 system is being used as a pattern copying device, i.e., the output 
 reference frame is identical to the input frame and no transformation is 
 performed. In the case where the input picture undergoes a transformation, 
 it is no longer true that the common input to all of the comparators will 
 be in exact correspondence to one of the reference levels.* In this case, 
 calling the common input X*, it is true that 
 
 X < X* < X . n 
 
 (^1) 
 
 since all of the analog voltages lie in the same bounded interval. Due 
 to Eq. (U.l) we can postulate that 
 
 F(x.) < F(x*) < F(x. n ) 
 o. - - j+1 
 
 (*.a) 
 
 Equation (U.2) may certainly not be true,' however, it is one possible 
 
 approximation for a functional value which is not available on our 
 
 input potentiometers . This approximation assumes that the total function 
 
 composed of the 32 F(x.)'s has no discontinuities in the 
 
 regions between any two reference levels. This is of course 
 
 a reasonable assumption. 
 
 MR 
 
 * The reason for this will not be explained here; however, the 
 subsequent discussion should be clear without it. 
 
-37- 
 One method of selecting a value for F(x*) is to assume that 
 
 F(x ) + F(x ) 
 F(x*) = — J-= 2±±- 
 
 (h.3) 
 
 Obviously Eq„ (U.3) is just a simple linear interpolation between 
 F(x.) and F(x. ), one approximation of the many that could be made. 
 
 The advantage of this approximation lies in its ease of 
 implementation. The system of Figure 21 is easily modified by the addition 
 of the voltage averaging network as discussed in Appendix B. The output 
 of this network for the case n = 2 is 
 
 V = 
 
 V + V 
 1 2 
 
 for r » R 
 
 It is clear that since the output of the ungated diamond will float 
 (assume the voltage of the common bus) the resistor network will appear 
 as two small resistors terminated in a very large resistance. It is also 
 evident that exact comparisons can still be made with this modification. 
 This modified look-up and interpolation system is shown in Figure 22. 
 
 In order to achieve the desired output of Eq„ (U.3) the 
 setting of rj ' (S) must be such that X* will compare to only two reference 
 levels „ Hence 
 
 V(s) < |x. - x | 
 
 will be satisfactory. 
 
-38- 
 
 ]" ,* 
 
 o 
 
 •H 
 
 -P 
 CO 
 
 H 
 O 
 
 ft 
 
 0) 
 
 c 
 
 H 
 
 In 
 
 O 
 
 «h 
 
 <D 
 
 •H 
 CH 
 •H 
 
 O 
 S 
 
 s 
 
 CD 
 
 -P 
 w 
 
 O 
 O 
 
 CAJ 
 OJ 
 
 b0 
 •H 
 
5. SUMMARY AND CONCLUSIONS 
 
 In this thesis we have attempted to present in some detail 
 the design of two useful analog-digital circuits. The particular 
 design criteria were derived from the requirements of the special- 
 purpose pattern-processing computer called Paramatrix. It is felt that 
 the circuit theory that has been developed is sufficient to enable the 
 reader to design modified versions of these circuits to fit his own needs. 
 
 It is quite possible that the reader's circuit requirements are 
 not as stringent as those of the Paramatrix system. In this case the 
 circuit design could become substantially simplified. For example, if 
 the signal levels to be gated by the diamond are small and/or a larger 
 offset than say 100 mv can be tolerated then clearly the constant -current 
 bias would not be necessary. 
 
 The reason for the use of Bypass- Gating for switching the 
 diamond is to avoid the necessity of using a large supply to turn off 
 the current -driving transistors. But Bypass- Gating is an inefficient 
 method of switching as it requires that the large bias-current 
 flow continuously. A more efficient method of gating can be achieved 
 by the phasing-splitting amplifier as shown in Figure 23 (with suitable 
 circuitry for driving the base of T from logic signal levels). With this 
 method power will be absorbed by the diamond gate only during gating time. 
 
 The analog comparator is a special purpose circuit. Most 
 comparator requirements are for threshold-type circuits where each 
 comparator circuit is set to "flip" at some preset level which is made 
 one of the inputs. Clearly the comparator circuit which is discussed here 
 will perform this function with a few simple modifications. 
 
 ■39- 
 
-ko- 
 
 v O 
 
 -v O 
 
 O-v 
 
 Figure 23 <. Phase-Splitting Amplifier, 
 
 The circuit applications which have been discussed are just two 
 of many applications of hybrid circuitry; they have been presented chiefly 
 for the purpose of tying-in the design discussions . Again these applications 
 are special purpose. 
 
 A word must be said concerning the method of analysis used in 
 deriving the circuit design equations. The seeming lack of the use of 
 equivalent circuits in our analysis (although we have used a very ideal 
 equivalent circuit) is easily justified. Our main interest is to design 
 practical circuits to meet specific requirements. Design equations for 
 such circuits can be derived by using less than ideal equivalent circuits 
 for our models; however, to get simple equations which can be realized, 
 one usually resorts to idealizing transistor parameters. We have used 
 this simplifying procedure as the starting point of our analysis. 
 
-kl- 
 
 Finally it is certainly worth noting that many interesting 
 extensions of these circuits could be pursued. For example one version 
 of a transistorized diamond has been discussed; if the expense can be 
 tolerated, the use of complimentary transistors (within a single case) 
 to form the input would make this a very versatile circuit. 
 
REFERENCES 
 
 [1] Korn, G. A. and T. M. Korn, Electronic Analog and Hybrid Computers, 
 McGraw-Hill, Inc., New York, I96U. 
 
 [2] Poppelbaum, W. J. and N. E. Wiseman, "Circuit Design for the New 
 Illinois Computer." Department of Computer Science, University of 
 Illinois, Urbana, Illinois. Report No. 90, 1959. 
 
 [3] Poppelbaum, W. J., etal., "Trance." Department of Computer Science, 
 University of Illinois, Urbana, Illinois. Report No. 73, 1956. 
 
 [k] Middlebrook, R. D., Differential Amplifiers , John Wiley and Sons, Inc., 
 New York, 1963. 
 
 Baker, R. H., etal., "The Diamond Circuit." Massachusetts Institute 
 of Technology, Lincoln Laboratory, Lincoln, Massachusetts. Technical 
 Report No. 300, 1963. 
 
 -1+2- 
 
APPENDIX A 
 
 Compensated Emitter-Follower 
 
 A compensated emitter-follower is essentially an amplifier with 
 unity voltage gain and current gain relatively equal to (3. There are a 
 number of different methods of designing such a circuit one of which is to 
 build a very high gain voltage amplifier and to reduce the gain to unity 
 by means of voltage feedback. Another method is to use conventional emitter- 
 followers in complementary connections and by means of current feedback 
 reduce the voltage offset of the circuit to zero. The former design 
 philosophy was used by M. Faiman in designing a compensated circuit for 
 Paramatrix. The resulting topology is shown in Figure 2U. 
 
 + 10v 
 
 Figure 2U. Compensated Emitter-Follower, 
 
 -U3- 
 
-kh- 
 
 Clearly from Figure 2h (again assuming ideal transistors) since 
 I and I are constant current sources, we have 
 
 J = *1 + *2 + H 
 
 and 
 
 h ml 3* h 
 
 Hence, 
 
 i =a constant 
 
 (A.l) 
 
 and the only circuit variation that must be compensated for is the 
 
 variation of V in the output transistors. This compensation is 
 achieved by the varying of the current i through R by means of the 
 differential amplifier composed of T\ and T in the feedback loop. 
 
APPENDIX B 
 
 Derivation of Resistor Network for Voltage Averaging 
 
 For the purpose of the derivation we assume the topology of 
 Figure 25. 
 
 Hence, 
 
 NODE 1 
 
 Figure 25. Topology for Voltage -Averaging Network, 
 
 Writing KCL at node (l), we have 
 
 srS(v, -v) 4 = ^?l -!v 
 
 R n * J 
 
 r " R n j R 
 
 V = 
 
 Zv. 
 n ,i 
 
 f R ^ 
 
 If we require in Eq„ (B.l) that r » R 
 
 V - - E V. 
 n n j 
 
 Therefore the output voltage becomes the average of the input voltages 
 
 -1*5- 
 
 (B.l) 
 
Unclassified 
 
 Security Classification 
 
 DOCUMENT CONTROL DATA - R&D 
 
 (Security classification of title, body ol abstract and indexing annotation must be entered when the overall report is classified) 
 
 1 ORIGINATIN G ACTIVITY (Corporate author) 
 
 Department of Computer Science 
 
 University of Illinois 
 
 Urbana, Illinois 61803 
 
 Za REPORT SECURITY CLASSIFICATION 
 
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 2b CROUP 
 
 3 REPORT TITLE 
 
 Hybrid Circuits for the Paramatrix System 
 
 4 DESCRIPTIVE NOTES (Type of report and inclusive dates) 
 
 Technical Report 
 
 5 AUTHORfS.) (Last name, first name, initial) 
 
 Prozeller, Edward F, 
 
 6 REPO RT DATE 
 
 August 1965 
 
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 12 SPONSORING MILITARY ACTIVITY 
 
 Office of Naval Research 
 219 South Dearborn Street 
 Chicago, Illinois 6060U 
 
 13 ABSTRACT 
 
 In order to design an analog/digital computer to perform pattern 
 processing, it became necessary to design precision analog and analog/digital 
 circuits. This paper discusses in detail the design of two hybrid circuits, 
 namely an analog comparator and an analog gate. The design of a compensated 
 emitter-follower is also described as are the applications of these three 
 circuits in the Paramatrix, pattern-processing computer. 
 
 -H6- 
 
 DD /,?„ 1473 
 
 Unclassified 
 
 Security Classification 
 
Unclassified 
 
 Security Classification 
 
 -H7- 
 
 14 
 
 KEY WORDS 
 
 LINK A 
 
 LINK B 
 
 LINK C 
 
 Paramatrix 
 Hybrid circuits 
 Bypass -Gating 
 Sensitivity selection 
 
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