LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN 510.84 I£6r riOoiaO-170 cop .SL The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN NOV 15 if" i 1973 wn L161 — 0-10% Digitized by the Internet Archive in 2013 http://archive.org/details/analysisoflongti168summ 6r , ] 6 8 DIGITAL COMPUTER LABORATORY u3 UNIVERSITY OF ILLINOIS URBANA, ILLINOIS REPORT NO. 168 ANALYSIS OF A LONG-TIME DELAY CIRCUIT FOR DIGITAL APPLICATION by James Erwin Summers September 21, 196^ (This report was submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering. ) DIGITAL COMPUTER LABORATORY UNIVERSITY OF ILLINOIS URBANA, ILLINOIS REPORT NO. 168 ANALYSIS OF A LONG-TIME DELAY CIRCUIT FOR DIGITAL APPLICATION by James Erwin Summers September 21, 196^ (This report was submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering. ) ACKNOWLEDGMENT The author wishes to express his sincere thanks to his advisor, Professor Gemot Metze and to Professor T. A„ Murrell for their advice and assistance in the preparation of this thesis. TABLE OF CONTENTS INTRODUCTION Page 1.1 Elementary Time Delay Methods ............... 1 1.2 Delay Generation with a Reversible Sweep ......... 3 2. THE DELAY CIRCUIT DESIGN .................... 5 2.1 A Delay Generator ..................... 5 2.2 The Astable Driver .................... 9 2.3 The Detector ....................... 10 2 ok- Resetting the Delay Generator 10 2,5 The Complete Delay Circuit ................ 13 3. A CONSIDERATION OF SECOND-ORDER EFFECTS ,,,,,,,.,,,, Ik 3.1 The Effect of Transistor Output Admittance ........ Ik 3.2 The Effect of Transistor Voltage Feedback ......... 16 3.3 Detector Current ..................... 17 k, THE DELAY GENERATOR CIRCUIT EQUATIONS ............. 18 4,1 The Delay Generator Differential Equation ......... 18 k.2 The Sweep Equations ...,.., ....... 19 5, A DELAY GENERATOR TOLERANCE ANALYSIS .............. 23 5.1 The Influence of Individual Parameter Variations 23 5.2 Worst Case Combinations .................. 35 6, CONCLUSIONS AND RECOMMENDATIONS ................ 37 6.1 Conclusions from the Tolerance Analysis .......... 37 6.2 Corrective Measures ...... ......... 37 6 . 3 Summary .......................... kl BIBLIOGRAPHY ....... .............. k2 APPENDIX .............................. k3 -IV- 1. INTRODUCTION 1.1 Elementary Time Delay Methods Delay of a pulse or level change by more than about one millisecond is most practically accomplished by a delay "device, " rather than a delay line This device would consist of a circuit of active and lumped passive elements. A very simple example of such a circuit is a resistor, capacitor, voltage sources, and a switch connected as in Fig. 1. When the switch is opened at FIGURE 1. A SIMPLE DELAY CIRCUIT FIGURE 2. RESPONSE FOR THE CIRCUIT OF FIG. 1. t = 0, a capacitor resting at an initial voltage, V., begins to discharge alon£ an exponential voltage -time path toward a final value, V , determined by the circuit. If a detector is attached to the circuit which will activate at some intermediate "pick-off" voltage, V , the delay time between the opening of the IT switch and the activation of the detector is T = -RC in V r- V P v f - v -l- ■2- One can apparently get any delay desired in this way by proper choice of V . The major disadvantage of this scheme, however, is that the time rate of change of the capacitor voltage decreases exponentially. The slope of the voltage-time characteristic at pick-off is dV u d tj = - (V - V )e" T//k T k v f V where k = RC„ The larger T is with respect to k, the smaller is the slope at pick-off, and the more sensitive the level detector must be for a given accuracy o On the other hand, to use only that part of the exponential with the steepest slope requires that (V - V. ) be a small part of (V - V.), and con- sequently that most of the supply voltage is wasted, from the viewpoint of delay generation. An obvious solution to this problem is to create a linear voltage-time dV function for timing instead of an exponential. For a given — at pick-off, the linear function of Fig, 3 requires a smaller (V - V. ) than does the exponential, and for the linear function, V may be placed anywhere between V. and V_ without change in the detector discrimination error. V. for linear sweep V. for exponential sweep FIGURE. 3> COMPARISON OF LINEAR AND EXPONENTIAL FUNCTIONS -3- The linear voltage sweep is used in the "one-shot" multivibrator timing circuit, where the base of the transistor which is off during the quasi- stable state follows a nearly linear path back to its turn-on voltage . One must note, however, that the linear sweep method ties the delay time, the sweep dV voltage range, and the slope, — , tightly together. Specifying an acceptable dV — and the power supply voltage puts an absolute limit on the length of the delay which can be generated. lo2 Delay Generation with a Reversible Sweep A longer delay and more economical use of the supply voltage could be obtained if the voltage sweep from V. to V were not constant in the same 1 p direction. By making the sweep partly retrace its progress a number of times, a long voltage sweep could be telescoped into a relatively small net level change, (V - V.). The proposed form of this sweep is illustrated in Fig. h. > t 2T 3T FIGURE h. THE REVERSIBLE SWEEP Each downward sweep of slope (■tt") 1 is followed by an upward recovery sweep of slope — , the net voltage traveled every 2T seconds being AV = dV\ /dV\ dtjl + \dtJ2_ assuming an equal time, T, for each sweep „ (Hereafter, AV will "be referred to as "delta, ") If N is the number of downward sweeps, »& + » - «(&* ■ v i V P The time interval for the entire sweep is (2N - l)T. Note that with this method, (V. - V ) and ("rrj-, can remain fixed, and it is yet possible to vary the delay time by changing delta. Similar ideas for producing time delay by discontinuous or reversible processes are presented in references 1 and 2, which deal with the pulse counting by magnetic cores,, The remainder of the thesis develops the design of a delay circuit based on a reversible voltage sweep and reports a tolerance analysis of a critical portion of that design. THE DELAY CIRCUIT DESIGN 2.1 A Delay Generator An alternating -rr can be obtained by alternately charging and dt discharging a capacitor with a current source. A circuit operating in this dV c fashion is shown in Fig. 5. The capacitor current I = -C -r— =1 - I , assuming the current, I,, drawn by the level detector is small before the pick- off voltage is reached. The common base output characteristics are very flat, so that if I , and I _ are maintained constant, I , and I _ will depend very el e2 cl c2 little on V . c The circuit is driven by a train of square waves which begins at the start of the delay period. When the input is at -12 volts, both transistors are on, with I greater than I . When the input is volts, only T is on, and the direction of the current through C is reversed. By adjusting R. and R , the rate of charge and discharge of C can be set so as to produce the desired saw-tooth approach of V to the pick-off voltage. The purpose of transistors T, and T is to provide linear voltage sweeps. Use of a resistor in place of T , for example, would result in an exponential upsweep such as in Fig. 2. To maintain linearity of sweep, neither transistor must be allowed to saturate during the delay interval. The config- uration has some built-in temperature stability due to the fact that a change in one collector current caused by temperature will be nearly matched by a corresponding change in the other collector current. The difference current through the capacitor will thus be affected less than the transistor currents. The delay generator will be designed to meet the following specifications : -5- -6- _ el "cl wv \w Input fu nct ion I I I t=0 T 2T H ■0 v 1 — -12 v 1* -12 vo VN/V bl Level Detector "c2 R Output "e2 "W 6 v. b2 R 5 > R 6 -12 v FIGURE 5.] THE REVERSIBLE SWEEP DELAY GENERATOR -1 -2 -3 ■11 h -12 l 2 3 k 13 14 15 16 17 1 , [-» , 1 1 , . — ^ Seconds Initial Voltage = -1.5 Detection level = -10. 5 Supply Voltage FIGURE 6. DESIRED DELAY GENERATOR RESPONSE dV c dt ■5 volts/second dV ~\ c dt = +^-.5 volts/second V. = V = -1.5 volts -10. 5 volts and V, , = -11 volts bl V^ = -1 volt b2 C = 20 uf supply voltage = 12 volts T., = 1 second d (T, = input square wave half -cycle duration. ) The design procedure is straightforward . av \ ( I . - I _ ) c\ cl c2 dt 1 = -5 I - I = 5 X 20 x 10" = 100 ua cl c2 L dt /2 C = ^.5 I c2 = 15 X 20 x 10 = 90 |ia -8- I . = I _ + 100 ua = 190 ua cl c2 Let the common base dc current gain for each transistor be Icl !90 , rtl X el = a^ = ~h = ±9k ^ i*-^-*- The emitter currents can also be expressed as V., - (-12) - V, , 1 - V. , bl bel _ bel el = E ± B. ± -V - V 1 - V _ b2 eb2 _ eb2 e2 ' R„ R„ For the low collector currents in the transistors, assume V n n and V , _ are bel eb2 both about .1 volt. Then 194 ua = 1 " — ■ and R, = k,65 K R 1 1 1 - .1 90 ua = ^ . _ and R = 9.8 K Choose R n = h.7 K, R = 10 K, and consider V^ . = „088 volts, and V ^ 1 2 bel eb2 = .082 volts. The bias for the transistors is provided by relatively low impedance voltage dividers by choosing R = 11 K, R, = 1 K, R = 1 K, and R^ = 11 K„ The delay time is nominally 17 seconds,, -9- 2.2 The Astable Driver The driver for the delay generator is an astable flipflop with an output amplifier. When the "start" input is held at -12 volts, T. is held just barely off. When the "start" input is raised a volt or two, T. is allowed to turn on, and the circuit runs as a normal, astable flipflop. A sharp positive starting edge should trigger T, on, so that the time delay is measured from the starting edge. A -12 volt level applied at the "stop" terminal will clamp T off and so stop the free-running action of the circuit. The output amplifier Output Level Detector * Delay Generator Stop Start T ■12 v FIGURE 7. THE ASTABLE DRIVER stage is used to reduce loading on the astable circuit, and this stage is driven from the emitter to escape the exponential recovery of the collector voltage of T, when T, turns off. The diodes in the emitters are used to provide enough -10- drop to turn the transistors off through similar diodes connected to the "base, using the available -12 volt level for turn-off,, The astable driver will be designed around the following specifica- tions: the duration of each state is one second, the collector current of the saturated transistor is 5 ma, the forward drop across the diodes is .5 volt, and the base -emitter voltage of the saturated transistor is .2 volt. From these specifications, FL = ° = 2.3 K, Use R^ = 2.4 K, so that ^ 9 5 ma 9 ' I i = ^T^7 = ^8 ma. When T turns on, V _ = -11.5. and V . = -11.3 - 11. 5 c4 2,4 K 3 ' c3— b4 = -22,8 volts. The equation for the base voltage of T, is then -t/R 12 C V , = -22,8 e T. turns on when V , reaches -12 volts. For the duration of the "off" state to be one second, R lp C o = ~1 — (10/00 A T = 1°55° To supply sufficient base current for T, , R, _ < —=r — - , where (3 is the common emitter dc 4 12 — 5 ma current gain. Assume that 3 > 50. For p > 50, R < 113 K, so that R = 100 K 1.55 is chosen. Then C = — = 15.5 l-if. The circuit is symmetrical, so i 100 X 10 J that C 2 = Cy R 1Q = R , and R ±± - R^ . 2.3 The Detector The pick-off device can be merely a transistor which turns on at a given base voltage, or a Schmidt trigger if a fast rise time is desired for the output pulse. The input impedance of the detector should he on the order of 10 megohms before pick-off. 2 . 4 Reset ting the Delay Generator After the completion of one delay period, the delay generator must be reset for its next use. Resetting is accomplished by allowing T_ to saturate, but at a different bias and current level than during delay generation. At the beginning of the next delay interval, T is switched back to its original bias. The resetting circuitry is shown in Fig. 8. -11- \X/ ft 12vO-W\A R 6 ' Rr Reset: v . . . ° — AAA- Operate : -12 v p T, \k ^Zt 1.5 v FIGURE 8. RESET CIRCUITRY FOR THE DELAY GENERATOR Start pulse >■ Astable Driver Start «e Reset pulse Reset Delay Generator Stop Level Detector Output FIGURE 9. DELAY CIRCUIT CONTROLLED BY AN EXTERNAL FLIPFLOP -12- When T^ is turned off by the volt reset level, the base voltage of T drops far enough to turn on T . The new bias is such that the resetting current, I , is much larger (about 5 ma) than the current through R , so that the emitters of T and T assume nearly the same voltage. When the capacitor charges sufficiently to saturate T , the collector of T comes to rest at the emitter voltage of -1.5 volts, which is V. „ After V reaches -1.5 volts, emitter current flows into the common base terminal, adjusting the base voltage to an equilibrium value near -1.5 volts. The size of R , determines the rate at which C is charged. The resetting current is chosen as 5 ma. At an emitter current of 5 ma, V , = .2 volt and I n = „06 ma, using 2N10Q transistor data. The total ' eb b ' D base current flowing into the common base terminal is then .12 ma. An "open circuit" base potential can be defined as R, , + 100 V = -12 -^ boc R l]+ + 1200 If V, = -1.7* R-, i =82 ohms. The base current makes negligible change in boc "14 base bias from V n . Resetting current is a sensitive function of R-, , , and too boc 14 7 large a value for R , can cause overstressing of T . During time delay genera- tion, T/- is held in saturation, shorting R , to ground and returning the base bias to T to -1 volt. Using the above design, V can be returned to -1.5 volts in 1/25 second. The minimum t ime between uses of the circuit is set by the driver, however, which requires one-half cycle, or one second, to return to its starting position. -13- 2„5 The Complete Delay Circuit Starting and resetting of the delay circuit may be accomplished with a flipflop anywhere in the over-all system. The connections for the complete circuit are shown in Fig. 9> where the "start" pulse sets the "l" side of the flipflop to volts and the "0" side to -12 volts. 3. A CONSIDERATION OF SECOND-ORDER EFFECTS The delay generator design assumed that the capacitor current depended only on the emitter currents of T, and T . A more complete analysis reveals that the capacitor current does depend on the capacitor voltage as well. The causes of this dependence are investigated to determine how much departure there will be from a truly linear voltage sweep. 3.1 The Effect of Transistor Output Admittance The common base connected transistor is not an ideal current source, since it does have some output admittance, A piece-wise linear "large signal" model of the transistor collector circuit, including output admittance, h , , ob is used to approximate more closely the real situation. The dc output admittance for the transistor will be chosen as the incremental output admittance evaluated at V = 5 volts. (See Fig. 11.) The slope of the output characteristic at V = 5 is an approximate average slope for the operating ranges of T, and T_, and it is the commonly specified value of h , given for transistors, ob Using the straight line approximation of Fig, 11 for the output characteristic, the transistor collector currents are evaluated as: I . = a,, I -. + (V ,, - 5)h , , cl bl el cbl obi and X c2 = ^2^2 + (V bc2 - 5)h ob2 Substituting V n , = 11 + V , and V, _ = -(V + l) into these equations gives D cbl q bc2 c -Ik- -15- -11 bl e O 1 i X o . cl _ c2 a b2 I e2 • r n = 1 h obi r^ = 2 h ob2 FIGURE 10. TRANSISTOR "LARGE SIGNAL" MODEL FOR THE DELAY GENERATOR (I = collector current) v c J > V 12 3 k 5 6 Volts 8 9 cb FIGURE 11. COMMON BASE OUTPUT CHARACTERISTIC FIGURE 12. THE EFFECT OF A CHANGING INPUT CHARACTERISTIC ON THE EMITTER CURRENT -16- I . - a.,1 , + (V + 11 - 5)h ,, = a,, I . + (V + 6)h ^ cl bl el c obi bl el v c obi and I _ = a, n I _ + (-1 - V - 5)h . - a, n I - (V + 6)h , _ c2 b2 e2 c ob2 b2 e2 ^ e ' ob2 The capacitor current is then I = I - I ,. = a, ,1 I - a, n I n + (V + 6)(h . . + h t/ J c cl c2 ; bl el. b2 e2 c v obi ob2 3.2 The Effect of Transistor Voltage Feedback The transistor input characteristic is a function of the base-collector voltage, V . The variation of the input characteristic as V changes has small effect in many applications, but in the delay generator, where currents are small, a normally small effect may be noticeable. The manner in which the changing input characteristic affects the emitter current and base-emitter voltage is shown in Fig. 12. The incremental voltage feedback ratio is eb h rb AV be I = constant e To estimate AI as V, goes from 1 to 10 volts, calculate e be and then let olO c3v AV 1, AI = - -^ e R -17- A straight line approximation to the plot of h , as a function of V, in the D rb be G.E. Transistor Manual yields h , = 1.Q1 h , V, ' . (h , is the value of h . rb rbo be rbo rb at V, = 5 = Henceforth, h , will be equivalent to h , = ) Then be rb rbo r 10 -.1*1 From this result, AI = — (=9)(9°3)h , = -8.37 h ,/_ . (h , must be derated from 7 e R rb rb/R v rb e ' e its commonly specified value at 1 ma by the factor = 9, ^or I = 200 ua, ) Making a linear interpolation of AI about V = 5 leads to the approximation, OK 1=1 - —- (V. - 5)h ,, where I is the emitter current at V. = 5 volts „ e eo R be rb 7 eo be e , For T, , V n = V + 11, R = ^J K. and h . = 3 X 10" , a typical value 1' be c ' e ' rb > j? of h , for the 2N335- Then I _ = I -\ - (,05^)(V + 6) where I . and I . are rb el elo c el elo in microamps. The variation in capacitor current due to voltage feedback in T, and T , as V goes from -1=5 to -10=5 volts, will amount to about 1 microamp= 3 = 3 Detector Current If the detector input is the base of a transistor which is off until pick-off, the base current drawn before pick-off will be at most about the I CO of the transistor. Letting this current be approximately 1 ua at V = -1=5 and at V = V = -10=5, the input impedance of the detector must be 10 meg- ohms, and the expression for the detector input current is V +10=5 h = ^~Td — ^ a k. THE DELAY GENERATOR CIRCUIT EQUATIONS h . 1 The Delay Ge n erator Differential E quation The capacitor current, I , may now be expressed in terms of all the parameters considered as I = I . - I c + I . c cl c2 d = a, , I -, - a, n I _ + (V + 6)(h , , + h , _) bl el b2 e2 c obi ob2 (v c + 6)(.8k) rbl rb2 - R l R 2 ■ v + 10.5 c 10 The emitter currents are calculated as and where T bias! bel _ , . , , „ ,_ ,, I . = — — — - -— — for a driver level of -12 volts el R I ., = for a driver level of volts el ^ V bias2 " V eb2^ "e2 biasl s R 3 + X sat and R 5 bias2 s Rj- + R/- -18- -19- A complete list of symbols used and the design values assigned to them are found in Table 1. (See also Fig, 5.) For a driver level of -12 volts, corresponding to a downsweep, substitution of the numerical values of Table 1 into equation 4,1a yields dV I = -C — § = 101.8 + ,25 V (4,1b) c dt c v For a driver level of volts, corresponding to an upsweep, equation 4,1a becomes dV I = -C —£ = -88 + ,27 V (4.1c) c dt c v ' 4,2 The Sweep Equations The general solution to the differential equation — — + bV = c is dt V = (V - £)e~ bt + £ (lj.,2) o b b where V is an initial value of V, From equations 4,1b and 4,2, the capacitor voltage during a downsweep is described by V = (V + kO r j)e - 407, where V is the starting point of the downsweep,, From equations 4„lc and ko2, the capacitor voltage during an upsweep is described by V = (V - 326)e ' + 326, Because second-order effects have made the sweeps exponential instead of strictly linear, the value of V after 17 seconds should be recalculated, A precise calculation of the saw-tooth path of V versus time calls for a lengthy calculation, since the beginning of one exponential sweep must be taken as the end point of the last sweep, A good approximate calculation which can be done by hand will be sought, -20- TABLE 1, BELAY GENERATOR CIRCUIT PARAMETERS Symbol Bescripxion Resign Value Common base dc current gain for T, ,98 Common base dc current gain for T ,98 Timing capacitor 20 uf Common base output admittance for T, ,2 \imho Common base output admittance for T ,k |j.mho -k Common base voltage feedback ratio for T, 3 X 10 -L i Common base voltage feedback ratio for T p 8 X 10 Emitter current for T, at V = -6 19^ |~ia Emitter current for T„ at V = -6 92 ua 2 c Betector input impedance 10 meg See Fig „ 5 ^J K See Fig, 5 10 K See Fig, 5 UK See Fig, 5 IK See Fig, 5 IK See Fig, 5 UK Transistor 1, See Fig, 5 Transistor 2, See Fig, 5 Duration of -12 volt driver level 1 sec Duration of volt driver level 1 sec Base-emitter voltage of T-. ,088 v Emitter-base voltage of T ,082 v Capacitor voltage to ground Supply voltage 12 v Saturation voltage of driver output v Scl"C a bl %2 C "obi h ob2 \bl h rb2 X el X e2 R d R l R 2 R 3 \ R 5 R 6 T l T 2 T dl T d2 V bel V eb2 V c V s V •21- To begin with, calculate the length of a downsweep to check how near the sweep length is to 5 volts, The equation for the downsweep is V = (v + 407)e _t / + 407o For t = 1 second, c v o -1/80 i, 1 1 ! ' = (1 - TvC + 2(80) 2 and (V c -T )- (V + ^07)(-8i + s ^) using only three terms of the Taylor series, For V = -1.5 volts, (V c - V o ) = W5. 5(- gS + STSoo) " -5-07 + .03 = -5.04 volts By the same method, the first upsweep is found to be h,hG volts in length. The lengths of the sweeps are near their nominal design values. With this information, the first downsweep will be considered to begin at -1«5 volts, the second at -2 volts, and so on at one-half volt intervals. The total voltage travel of nine downsweeps beginning at these starting points will be com- pared with a similarly computed total of eight upsweeps beginning at -6„5 volts, -7 volts, etc. The difference in the two totals will be the net voltage traveled by the capacitor voltage in 17 seconds. For the nine downsweeps, total downsweep = [(^4-07 - 1-5) + (^07 - 2) + ... + (1+07 - 5»5)](- 35 - jTrgoo) = -45.12 volts For the eight upsweeps, -22- total upsweep = [(-6.5 - 326) + (-7 - 326) + ... + (-10 - 326)](- ^ + j^~q) = 35-81 volts The net travel is -45.12 + 35° 81 = -9° 3 volts. After nine downsweeps (or 17 seconds), the capacitor voltage is -1.5 - 9-3 = -10 ,8 volts. The pick-off voltage for a 17 second delay should be located midway between the end points of the eighth and ninth downsweeps, in this case at about -10.5 volts. For detection on the ninth downsweep, the longest delay is then 17 seconds, and the shortest delay is 17 - .5 volts/5 volts per second, or 16.9 seconds. 5, A DELAY GENERATOR TOLERANCE ANALYSIS The predictability and reliability of any circuit depends upon its sensitivity to deviations of components from their design values , To deter- mine the effects of component tolerances on the time delay circuit, a complete tolerance analysis has been done on the delay generator , (Since the astable driver is a standard circuit, tolerance limits for its components are considered to be known, ) The analysis consists first of plotting the time delay as a function of variation of each parameter alone, with all others being held at design values, and then combining parameter variations into several "worst case" conditions., 5«1 The Influence of Individual Parameter Variations Due to the repetitive labor involved in the calculation of the delay generator's saw-tooth response, the tolerance analysis problem was programmed for the IBM 7094 computer in the FORTRAN language. The calculation of time delay as a function of individual parameter variation was done using five separate programs, with each program investigating from one to four parameters. The programs used in this report are described in detail by flow charts in the appendix. All of the programs have basically the same organiza- tion, and all are based on equations 4,1a and 4,2, The capacitor currents for upsweep and downsweep are evaluated in terms of the parameters of interest, which are expressed explicitly as variables in the program. The constants of the upsweep and downsweep exponential equations are in turn evaluated from the capacitor currents and the parameters expressed as variables. The downsweep exponential equation is used to calculate the end point, V , of each downsweep by starting the downsweep at the end point of the last upsweep. Similarly, the end point, V , of each upsweep is calculated using the end point of the last ■23- -2k- downsweep as the starting point for the upsweep. The calculation of the exact saw-tooth path of V is an inner loop of the program, which successively evaluates V n and V until V, becomes more negative than the detection level of dud -10. 5 volts. At this time the program prints the end point of the last down- sweep, the voltage difference, "delta, " between the last and next-to-last downsweep end points, the number of downsweeps made, and the values of the variables used in the calculation. One or more outer loops is used to incre- ment one variable at a time and transfer to the beginning of the calculation sequence. The first two programs relate time delay to collector currents I "cl and I _, respectively. From equation 4.1a I = -^ cl R V (1 — — ) - V - V s v R + R, ; sat bel 3 k To calculate the percentage deviation in a single parameter (e.g., R ) which causes a given percentage deviation in I , the relationships of Table 2 are applied. Thus, a knowledge of time delay in terms of a circuit current can be transformed to time delay in terms of individual parameters. With the exceptions of h ,,, h n ^, and V ,, the calculated time obi' ob2' sat' delay as a function of each individual parameter is plotted in the graphs of Fig. 13 through Fig. 22. The "per cent deviation" on the parameter axis indicates deviation of the parameter from its design value of Table 1. The staircase shape of the plots is caused by the number of downsweeps between -1.5 volts and -10. 5 volts changing as the parameter changes. The flat tops of the steps are not actually flat, but tilt by about .1 second in the "down- stairs" direction. The plots show that a deviation of + 1/2 per cent in transistor gain or in any resistance value will cause a two-second error. Other limits of -25- TABLE 2. PERCENTAGE RELATIONSHIPS Per cent change in the Parameter causing a per cent Expression Parameter change "p" in the Expression ab 1 a a + b a + b a - b a - b a 1 + p/. 100 p(l + 1 a/b) 1 - p 100 a b -p(l + , a/b) 1 + p/. 100 -p(a - b) b p(a - b) ■26. t3 a o o oj co •H >> cd H 0) n § •H EH 3^567 Per Cent Deviation in a, , or R, bl k FIGURE 13. TIME DELAY AS A FUNCTION OF el, AND R, -27- CO xi a o o CD CO •H >> cd H I •H EH -7 -6 -5 -h -3 -1 Per Cent Deviation in R or R FIGURE Ik. TIME DELAY AS A FUNCTION OF R AND R -28- o o CD 03 H ■H Eh -70 -60 -50 -40 -30 -20 -10 10 20 30 40 Per Cent Deviation in V, , bel FIGURE 15. TIME DELAY AS A FUNCTION OF V. bel -29- w o V > a5 rH I •H EH 17 15 13 11 1 1 1 1 1 i 1 1 1 1 1 1 1 k 6 8 10 12 Detector Impedance in Megohms Ik FIGURE 20. TIME DELAY AS A FUNCTION OF THE DETECTOR INPUT IMPEDANCE -33- CO o o >> cti H 0) Q § •H EH 33 h 31 29 27 25 23 _ L_ 21 — 19 - 17 15 13 11 L One Driver Cycle ■12 dl "d2 T,-, (T,- = 1 second) dl d2 T jr , (T nn =1 second d2 v dl H T „95 .96 ,97 .98 ,99 1.00 1.01 1.02 L03 1.04 1,05 T 1.05 1.04 1.03 1.02 1.01 1.00 .99 .98 .97 .96 ,95 Seconds FIGURE 21. TIME DELAY AS A FUNCTION OF DRIVER HALF-CYCLE TIMES -34- 25 —i 23 CO T5 21 PI O o > 03 H 17 « 0) F* •H EH lb 13 11 -16 -12 -8-4 h 8 12 16 Per Cent Deviation in Supply Voltage FIGURE 22. TIME DELAY AS A FUNCTION OF SUPPLY VOLTAGE -35- individual variation are + 3 per cent for the capcitor, + 2 per cent for the supply voltage, + 5 milliseconds for driver half-cycles, and 6 megohms or above for the detector input impedance. Either transistor output admittance can be varied from to 2 (j,mho without causing the number of downsweeps to change . An increase in driver output transistor saturation voltage from to .01 volt causes the delay to increase from 17 to 21 seconds, A V of .04 volt results in a time delay in excess of 80 seconds, 5.2 Worst Case Combinations Program 6 (see Appendix), which expresses all the circuit parameters explicitly as variables, can calculate the delay time for any combination of values of the circuit parameters. This program was used to calculate the delay time for "worst case" combinations of circuit values for both too-long and too-short delay, A worst case combination for a too-long delay was created by causing each parameter to vary in the direction in which it individ- ually caused a too-long delay. The same method was used in selecting the worst case for a too-short delay. The parameter variations and resulting time delays for each case are enumerated in Table 3° The table includes a worst case combination of resistors only for both too-long and too-short delay. In truth, there is only one "worst case" combination of parameter deviations. What are referred to as "worst" cases in this thesis are more correctly called "bad" cases, and these are chosen for study because of the difficulty of determining precisely the absolute worst case for the delay generator. -36- TABLE 3, WORST CASE COMBINATIONS Too-Short I Delay Too-Long Delay Case 1 Case 2 Case 3 Case h Parameter io Variation $ Variation +1 $ Variation 'fo Variation a bi -1 %s -1 +1 c -3 +3 h obl -100 +6oo h ob2 -100 +125 h rbl h rt,2 R l -1 -1 +1 +1 R 2 +1 +1 -1 -1 R 3 -1 -1 +1 +1 \ +1 +1 -1 -1 R 5 -1 -1 +1 +1 R 6 +1 +1 -1 -1 R d -50 +50 T dl T d2 V bel -5 +5 V be2 +5 -5 V s +3 -3 V , sat Time delay 9 sec 5 sec over 200 sec indefinite NOTE: h „ ., , h ^, T n .,, T,„, and V have not been included in the rbl' rb2 dl d2 sat worst case analysis. 6. CONCLUSIONS AND RECOMMENDATIONS 6.1 Conclusions from the Tolerance Analysis The delay generator is essentially a counter of the astable driver cycles, and its function could be performed by a conventional bistable flip- flop counter. The most apparent advantage of the proposed delay generator is its economy of circuit components, for a conventional counter would require four flipflops to count more than eight driver cycles . The tolerance analysis shows, however, that the proposed circuit is too sensitive to circuit element variations to count reliably as many as eight driver cycles . Of particular importance is the fact that a time difference in the driver half- cycles can result in a larger time error, due to change in the number of downsweeps, than the cumulative error over several cycles which would occur using a flipflop counter. Improvement in the design must be made if the proposed scheme is to be acceptable. 6.2 Corrective Measures The simplest corrective measures involve changes within the present circuit configuration. It is first recommended that the voltage supply be increased relative to the range (V. - V ). This will allow the base voltage l p of T, to be fixed farther from the downsweep driver level and the base voltage of T to be fixed farther from ground. The increased bias voltages will make the emitter currents less sensitive to changes in base-emitter voltage and the driver saturation voltage, V sat Making delta larger than its present value of one-half volt is another simple beneficial change. A delta of approximately one volt is obtained for I = 180 ua and I = 80 ua, Using these design values, Program 7 investi- gated the time delay as a function of variation of I , about the design center ■37- -38- value of 180 \ia.o A comparison of the sensitivity of delay to variation in I cl for this new design to the sensitivity of the present design is made in the plots of Fig. 23. Though increasing delta to one volt makes the circuit four times as tolerant to variation in I , the total delay time is cut to nine seconds, and much advantage is lost over the flipflop counter . The manner in which variation in the capacitor, C, affects the delay time suggests a desirable change in the delay generator's operation. Because dV c the magnitude of -77— for both upsweep and downsweep is inversely proportional to C, a change in C causes the same percentage change in both upsweep and downsweep slopes . This compensating effect explains why the circuit is less sensitive to C than to the resistors. If a change in the downsweep slope could always be accompanied by a proportional change in upsweep slope, the circuit would be all-around less sensitive to parameter change. The upsweep slope can be tied to the downsweep slope by making the capacitor current during the up- sweep always proportional to the capacitor current during the downsweep. Program 8 uses the same design values as Program 1, but effectively calculates the upsweep current as upsweep capacitor current = ttt; — q (downsweep capacitor current) (The ratio of 88/101,8 is the design center ratio for the present circuit.) Program 8 varies I , in the same fashion as Program 1, and the results of the two programs are plotted for comparison in Fig, 2^, An obvious ability to withstand component change is gained using a proportional current scheme, but the gain would probably be offset by the complexity of the feedback needed to bring it about , -39- 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9- 7- L_ 1 I I delta = „5 volt delta = 1 volt ■7 -6 -5 -4 -3 -2-1 1 Per Cent Deviation in I , cl 3 h FIGURE 23 . TIME DELAY AS A FUNCTION OF I . FOR TWO VALUES OF DELTA cl -1+0- CO O o CD CO cd H V End point of a downsweep V End point of an upsweep -k 3 - Variable cl Variable "c2 ■kk- PROGRAM 1 Range 190 ua - 3„6fo to 190 (j.a + Machine time: .3 minute PROGRAM 2 Range 90 ua - 16.7$ to 90 ua + 3„9$ Machine time: .2 minute Increment .19 ua = .1° Increment 09 ua = .1$ Comments: I is increased by .09 increments from its design value of 90 until I = 93- 5. I p is then reset to 89. 91 and decreased by decrements of until I _ = 75 c2 PROGRAM 3 Variables Range V s 10 to Ik volts R a 1 to 20 megohms C 15 to 22 uf sat to .Ok volt Machine t: Lme : 1 minute Comments : This ] urogram was run twice, once i Increment .12 volt = ] 1 megohm .1 uf = .5/0 .01 volt design values to the upper limits of their ranges, and once decreasing the variables to the lower limits of their ranges . The flow chart shows the positive increment run. The negative increment run simply 45- PROGRAM 3 (CONT'D) subtracts the appropriate increment each time through the loop until the lower end of the variable range is reached, V - R, . se' de> C , and V are indices which record the highest (or lowest) e' sate values attained by their corresponding variables during the program run, V must be limited to .Ok to avoid an infinite calculation sat in the inner loop. PROGRAM k Variables h obi h ob2 Machine time Range to 2 u.mho to 2 |_imho Increment . 1 umho . 1 umho .k minute Comments: This program was run twice, once with h , held at its design value and h __ incremented, and once with h __ held at its design value ob2 ob2 and h , ., incremented. The flow chart is for the latter case,, obi PROGRAM 5 Variables T dl T d2 Machine time Range .95 to 1.05 sec .95 to 1.05 sec Increment ,002 sec ,002 sec .h minute Comments T,, and T.,^ are indices which record the highest values attained die d2e by T and T during the program run. -k6- PROGRAM 6 Machine time : . k minute Comments: The variables for this program are listed, in Table 3, as well as the numerical values used. Each set of values for the variables is read into the program from data cards. The program will process any number of sets of values for the variables. Variable "cl PROGRAM 7 Range 180 - 8.2$ to 180 + Hi Increment 18 ua = .1$ Machine time: ,k minute Comments: The flow chart for this program is basically the same as the chart for Program 1. The variable, I , is incremented in steps of .18, rather than .19, between 164.88 and 200. L.^ is calculated as diff 1=1 - 78.2, and the exponential upsweep equation is V = (V^ - 289)e _1 ' lk + 289. u d PROGRAM 8 Program 8 is identical to Program 1 except that -1/80 V = (V - 3.21 )e u l d 3 diff ; + 3° 21, . „ „ is the upsweep exponential equation. The appearance of I . in this equation arises from the condition that the upsweep capacitor current must remain proportional to the downsweep current, 47- PROGRAM 1 Initialize I , cl I = 183.16 -> Initialize V,, V , N d u V u = -1.5 v d - -1.5 N = I diff * I cl 88,2 V dt = tV u + Ml diff )]e Delta = V J4 - V. dt d •1/80 * Initialize V , V,, N u d V u - -1.5 v a = o N = I. -^ = 191 = 8 - I diff y c2 1 v, = I ~ 2 chrge c2 V dt = ^^W^ Delta = V dt - V d V d " V dt ■i/8o Mi diff) C = C e -> V = V sate sat (intermediate steps; see following page.) V,. = (V + A)e dt u Delta = V„ - V, dt d d dt -1/k, PRINT V,, N, Delta, V , R., d s d C > V sat' I cl^ J c2 A + < B)e + B V = u ^d" V = V + .01 sat sat -50- PROGRAM 3 (CONT'D) Intermediate Steps for Program 3' V = -1.5 u v a = o N = I cl = 208 o 5(.083(V s ) - V sat - ,088) l c2 = 98(.083(v s ) - .082) k ± = c/(.15 + l/R d ) K 2 = c/(.17 + l/R d ) A = k l (l cl " J c2 + ° 75 + 10 -5/R d )/c B = k 2 (l c2 - ,95 - 10.5/R d )/C -51- PROGRAM k Initialize h obi obi h m = - k ob2 Initialize V,, V , N d u v a = o V u = -1.5 N = I d . ff = 100.36 + 2.4(h obl + h Qb2 ) W ■ ^ M - S - U(h obl + h ob2> k l= 2 °/[- U ( h obl +h ob2 )] k 2 -20/[.Mh obl + h ob2 ) + .03] A-i^i^/ao B = k_(I , )/20 2 chree , -l/ki V dt - (V + A)e ■ - A <: Delta = V,, - V, dt d V = V a dt N = N + 1 PRINT V,, N, Delta, h . . , h . _ d obi ob2 0,+ V = (V d - B)e -1/K + B -i'V -52- PROGRAM 5 Initialize T,,, T in dl' d2 T dl " "95 T d2 = 1.0 S = T = T die dl T = T d2e d2 V u V -1.5 -1 = 5 d N = V,. = (V + 407,2)e dt u Delta = V -V 80 ^07.2 <- , " V d V = V d dt N = N + 1 PRINT V d , N, Delta, T^, T d2 V = u (V d 326 )e ^ + 326 0, I Reset T T_ = T, n + ,002 dl dl S = S + 1 T d2 =T d2 +S (' 002 ) -53- PROGRAM 6 Read from data cards : R^ R 2 ' R y \> R 5^ R 6' V s' R d ? C ' h obl' h ob2' h rbl' h rb2' Vl' a b2' V bel' V eb2 PRINT V biasl = V s (l - R 3 /(R 3 + V } V bias2 = V s ( V (R 5 +R 6 )) I . = a. , (V, . , cl bl biasl I c2 :: a b2^ V bias2 Vi' V. be2 F = .0836(11^/^ + h rb2 /R 2 ) J dlff ■ X 1 - X c2 + 10 ^ /R d + 2A(h obl + h oK> - 6F W ■ \2 - 2 - U(h obl + h ob2> + 3 - 5F " 10 - 5 / R d k„ " c/lMK^ + \ b2 ) - f/1-7 + i/R d ] 2 obi A = VW/c B = MW^ T = V = V = u = -1.5 v dt - (v + u A)e Delta =' V^ dt - v d V = v dt N ■ N + 1 l/k 1 - A R^ R 2 ' R 3^ R V R S> R *bl' *b2' V R d> C > V d , N, Delta, I , 1^ V = (V. - B)e u d ■l/k. + B