LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 no.764-7\SSSS'^ ^ ciisa ^2:^ S555S :^^^^ ssss ?777771 ^S^ ^^\\\^^ SSS ^S2S; 2 o o _l m 3 tn I/) -M a. 0) o to -M to s- 00 o to fO CO 0) CT o -I OD OD 00 CVJ m I < CJ m im by two wires; one wire is the sign of the Burst according to its logical level and the other contains the usual Burst for the magnitude. An al- ternate representation might be the biased representation where is re- presented by 0.5, 0.5 by 1.0 and -0.5 by 0. In Reference 2 it was shown that the use of Block Sum Registers (BSR) simplified the averaging of Bursts and the performance of addition and multiplication of unsigned Bursts. However, those simple operations would not be simple any more if signed numbers were introduced. Addi- tionally, it was felt that an effort should be made to design the arith- metic unit out of standard logic circuits so that a comparison of BSR de- sign and standard logic design can be made. Therefore, the whole design of the arithmetic unit was based on standard logic design . A discussion of BSR design is included in the Conclusions chapter. BURSTCALC includes an arithmetic unit, which consists of an adder, subtractor, multiplier-divider, sign generator and an output counter which generates the result in Burst form, a timing generator which provides all the necessary timing signals to the machine, two in- put Burst generators which provide the Burst inputs to the arithmetic unit and, finally, a display for the result. The first part of this thesis describes the general ideas be- hind the arithmetic unit and their hardware implementations. The second part provides a detailed description of the remaining circuitry, fol- lowed by a few conclusions. 2. THE ARITHMETIC UNIT 2.1 Burst Adder The adder has to be used when addition is selected and the Bursts have equal signs or when subtraction is selected and the Bursts have opposite signs. Clearly, the resulting sign is always the sign of the addend A. The logical equations for the adder enabling signal (ADDENA) and the output sign (SO) are: ADDENA = ADD • (SA«SB) + SUB • (SA©SB) SO = SA where SA and SB are the signs of A and B, respectively. To prevent overflow a scaling by a factor of 2 is used so that the actual result is (A+B)/2. The principle used in the adder is that in one block period (10 time slots) the odd pulses of A-Burst and the even pu-lses of B-Burst are counted. Then the count is switched so that in the following block per- iod the odd pulses of the B-Burst and the even pulses of the A-Burst are counted. Obviously, the final count gives the sum of half of all the pulses in two consecutive blocks of A and B which is exactly (A+B)/2. This is shown in Figure 2.1. The realization of such an adder is very simple as shown in Figure 2.2. The only disadvantage of this adder is, as shown in Figure 2.1, that in certain instances the output Burst is not "compacted," i.e., not all the ones are at the beginning of the block. This disadvantage vanishes if a counter is used to count the output o h- o UJ UJ fVI m m - or >- •4-) UJ _l 3 > UJ UJ > CO H fO in O UJ UJ <+- »- Q. o < (/) o t- UJ lO tr +J UJ o CO r Q r— < O fO I cr o UJ Q. OJ (VJ )^ ^ CO o o _i ZJ o (.} CD z •r— < z Ll- O UJ CM (n ^ >- o »- liJ h IT UJ »- »- U. (/) it to UJ 2 Q _ o q: 5 w A ^=?=> A A UJ o - u -J CO -1 s_ < 4-> O =s < oo Crt ro a: CM UJ u. u. (U D s- CD 3 CT> z AAA o UJ :^ d^ 0) o o -1 o o 3 -I -1 o. o u o 2 z < UJ Ul o t- 1- -1 (0 (0 >- >- (O v> 10 this subtracter actually calculates the average of differences; however, as in the case of addition, there is no difference between the two calcu- lations , so that the final result is correct. 2.3 Burst Multiplier-Divider The multiplier and the divider are discussed together in this section simply because they use almost the same circuitry. Division, e.g., A/B, means finding how many times B is included in A, or in Burst Processing, to count the pulses in the A-Burst and, whenever the number of pulses is a multiple of the magnitude of the B- Burst, to add one to an output counter. If this conting continues for a 10-block period, the output counter contains A • 10/B. For example, if A is 0.6 and B is 0.3, then after every 3 pulses of the A-Burst a count- ing pulse is sent to the output counter, i.e., every block of the A-Burst causes two output counter pulses. If the counting continues for 10 blocks then the counter contains 20. This result, when averaged over a superblock, gives 0.2 after appropriate scaling. Clearly, the full range of the quotients is 0.1 to 10; therefore, scaling by 10 is required and this can be taken care of in the process of averaging. Figure 2.4 gives an illustrated explanation of the above idea. For the hardware implementation of division we use a modular shift register (MSR). The input to the MSR is the A-Burst which shifts ones into the MSR whenever a pulse occurs in the A-Burst. A special com- parator detects those instances when the contents of the MSR are equal to the magnitude of the B-Burst and causes the clearing of the MSR, while n T^TTTT ES ;\ssss ^::::c::.\ ^^ iSsss S^55 ^ ^ 1\'1\\' sss sSSSs :^SS ^■'<:r:\] 5?^? ss^ S\\\\N s^s ^ ^ss sssss CSS] sss In T^ :?:? rcct^t ssss SSSsi S^SS ^ y '•;;;; r'ToT 5^ ^ ^ ssss T^VT^S ssss K2:ra 2SS2 sssss ^ ^ sss ^ SS-2 d ID (/) UJ oc Q UJ < o CO to Ul OT 0. C£> ro CO O O O 1- Q. 1- II < II 11 5SS \\\N\S ss ^ SSS ^ SSs S^^ S5^ ^ ^ ^ 5^S no:! rc^r^ ^ ^ ^ sssss Ssss r^- ">'i . \\>,\a' ISSS21 ^SSSS :^2^ i:.:.:...:.i \\\\\N S^^^ ,\\\\\^ XKKKK' K^" -V'-1 ^SS S^ ESS2S 6 II < S555S sssss ;2^^;^ S^S5 R.:.:.:.;:^ S:S2 \\'>.\\\ ^ r:;,:.:,v3 ^^^ ?5SS5^ ^ ^^2 ^ iSS 222^ 'vWW ^ x\\\V O Ul ^ ro O III O X II o GQ 1- m OQ 5SS5 ' xXVw ^SSS S2SSS SS22 S\\\\> SSSSS \\\\v ^s s^ :ss5S ^ I- H o 00 I— < d 11 00 o o o c: •I— s- Cl. s- 0) T3 D tn UJ cc cn 12 sending a counting pulse to an output counter. Obviously, the MSR is a special counter which can change its modulus according to the magni- tude of the B-Burst. As described above, the A-Burst is used to shift ones in the MSR and this is done with no buffering, thus the A-Burst can be used ON- LINE. However, for the comparator to be able to compare the two Bursts, the B-Burst should be stable as an input to the comparator for at least one block period in order to have the value of the B-Burst known to the comparator. Consequently, ON-LINE input of the B-Burst is not possible and a buffer is required which holds the Burst long enough for the com- parator to operate correctly. This buffer should be updated fast enough by new versions of the B-Burst; a possible solution is to load the buffer every 10 clock periods so changes in the B-Bijrst can be taken account of and almost ON-LINE operation is achieved. Multiplication, in Burst Processing, can be as easy as the counting of the number of coincidences between the A-Burst and the B- Burst; the incoming bits of the B-Burst are checked and if a one is de- tected the A-Burst is sent to the output counter. If a zero comes in, a string of 10 zeros is sent to the output counter. This is shown in the second part of Figure 2.4. In order to check all the B-Burst bits against blocks of the A-Burst, it is necessary to staticize the B-Burst in a buffer, so that each block of the A-Burst is checked against a different bit of the B-Burst in the buffer. Consequently, the A-Burst can be used ON-LINE, but the B-Burst cannot. Additionally, the overall computation period necessary is 10 blocks, if all the bits of the B- Burst are checked. 13 The same comparator used for division, with a very small change, can be used now to select one bit out of the ten bits of the B-Burst, and this bit can then be ANDed with the ON-LINE incoming A-Burst. Every block period a different bit of the B-Burst in the buffer is selected. Therefore, the result is complete after 10 blocks. The actual counting is done by the output counter which counts the ANDed A-Bursts. An overall block diagram of the multiplier-divider is shown in Figure 2.5. Note that the B-Burst buffer is composed of two shift reg- isters; this is so because the B-Burst comes in serial form and should be assembled and then loaded into the buffer itself. Note, also, that the buffer is updated every 10 clock periods (or every block period) in either multiplication or division; this provides a fast response to any changes in the B-Burst. In multiplication it means that in each block period the B-Burst bit checked is taken from an updated B-Burst and al- most ON-LINE operation is achieved. All the registers are 10 bits long. The actual selection of bits from the B-Burst buffer is done by rotating a single one in the MSR so that only one bit can be selected by the com- pare-select logic. This one moves every 10 clock periods, as shown in Figure 2.5, and so a different bit of the buffer is selected at 10 clock-period intervals. The compare-select logic utilizes the important fact that all the pulses in a Burst are at the beginning of the block so that the size of the Burst can be found, simply, by looking for the 1-0 combina- tion. There are two exceptions, a Burst consisting of all zeros or ID (t a. uj n 14 s- u o i. ■o > •r" Q a; »—• Q. •^ ■M CsJ 15 all ones. In the latter case the last bits indicate the size of the Burst immediately. A detailed scheme of the compare-select logic is shown in Figure 2.6. The inverter on Bl is used to indicate that the B-Burst is equal to zero, and therefore division is impossible to per- form. In this case a stream of clock periods is sent to the output, so that the result is as big as possible. For the compare operation, used in division, each bit B. is ANDed with the next bit, B.^, , and with bit A., for i = 1 to 9. Only one combination of the two bits, B. • B.^,, can be high at one time, hence, enabling the corresponding A.. If the B-Burst is equal to 1.0, or BIO is high, then the AlO is selected directly. All the ANDs are ORed to form the output. For the select operation, used in multiplication, all the B. 's are blocked by the NANDs; therefore, each AND ANDs a bit B. with a bit A.. Recall that in multiplication only one A. is high at one particular time; consequently, only one B. is selected and appears at the output. In multiplication or division the sign of the result is inde- pendent of the magnitudes of the Bursts and is the EXCLUSIVE-OR of the signs of the Bursts. As described earlier the main idea in Burst Processing is the ON-LINE or almost ON-LINE low precision calculation with a higher preci- sion gained by averaging over more Bursts. A careful examination of the multiplier-divider shows that the operations actually performed are averages of products or averages of quotients where the required opera- tions should be the product of averages or the quotient of averages . 16 3 a. :^ 00 CD m 0^ is> uj m u. u. CO CO CD IS CD A > o O 0) 03 CL o o CM Ol O) 17 These quantities are different if the Bursts are not constant. This is, clearly, a disadvantage of the multiplier-divider, but, this disadvan- tage may be overcome by using constant or slowly changing Bursts. For multiplication one solution could be to hold the B-Burst constant for a superb! ock and to AND the A-Burst with all its bits. Then B-Burst changes to a new value and, again, the A-Burst is ANDed with all its bits, and so on. In this manner the sum of the products becomes equal to the product of the sums of the two Bursts since B-Burst is con- stant over all the computation period. If the result is extracted by averaging over a superblock, it represents the exact product. If a longer time is used, for a higher precision, then an error occurs, which depends on the magnitudes of the Bursts. This error can be kept arbitrar- ily small by restricting the amount of change of the B-Burst between superblocks and by restricting the time necessary for the averaging. For example, let the actual unit built be considered. The computation period is 10 blocks and the output period is 10 blocks, too, in order to repre- sent 1 percent precision numbers which result from the multiplication or the scaled division of two 10 percent precision Bursts. The output, if averaged over a superblock, is exact to 1 percent with the restric- tion for the B-Burst to change at intervals of superblocks only. If averaging is performed over 2 superblocks, an error results as shown in the computation below: (ZAl) If Bl - B-Burst in first superblock — tq Averaged A-Burst during first superblock 18 (IA2) B2 - B-Burst in second superblock -y^r Averaged A-Burst during second superblock then the required average over 2 superblocks is: Bl + B2 1/^^^ . ^^^ 2 ' 2^ 10 "^ 10^ and the actual result is: 1 lAl IA2 |(B1 . _ . B2 . ^) The error is the difference between the two results. If B2 is taken as Bl + £, the expression for the error can be reduced to Error = ^([Al - lA2) The maximum of this error depends on TAI , J'A2 and e. Since the maximum of the Burst magnitude is 1.0 and the minimum is 0, the expression for the error reaches its maximum when JAI is maximum, or 10, and when [A2 is minimum, or 0. The relation between the error and c becomes: Error = e/4 If we restrict e to 0.1, which is the minimum change in 10 percent Bursts, then the maximum error, when averaging over 2 superblocks, becomes 0.025. This is not a bad error at all, considering the fact that averaging over 2 superblocks intends to achieve 0.005 precision. For the averages for the A-Burst we have taken the extreme values of 1.0 and which is a very rapid change that will not usually occur. Therefore, the error is. 19 actually, less than the maximum calculated. As discussed earlier, the error can be further reduced by restricting e more so that the B-Burst changes at a slower rate. For division the same restrictions on the B-Burst can be used, namely keeping the B-Burst constant over the computation period and changing it only at intervals of this period. A similar derivation for the error introduced in the computation because of the difference between average of quotients and the quotient of averages of the two Bursts ap- plies, as shown below. Using the same definitions for the values of the B-Burst and the averages of the A-Burst as above, we find that the re- quired result of averaging over 2 superblocks is: liAl IA2 2^ 10 10^ in Bl + B2 10 • p — ^ and the actual result is: lAl ^A2 1 / 10 + 10 . 2 ^ lOBl 10B2 ' Using B2 as Bl + e, again, where c is the amount of change in B-Burst be- tween the superblocks, the error can be calculated. The expression for the error is: Error 200 ^ Bl + e/2 " Bl " Bl + £^ If e is kept yery small with regard to B, e.g., e < 0.1 and B > 0.5, then the approximation 20 ' =1-6 1 + 6 can be used. The expression for the error, after the following substi tutions, 1 ._ 1/, e and Bl . I '° ^'^ - 5BT' Bl + £ ^° Bl^^ " Bl^ becomes Error - 200 ^ Bl ^^ " 2B1^ " Bl " ~BT ^^ " BT^ ^ This expression can be reduced to: Error = "- J ll\2 - J;a1) 400Br If e and B are kept as above, the maximum error is: 1050 (1*2 -lAl) and for the extreme values for JA2 and J^Al , which are 10 and 0, respec- tively, the maximum error becomes 0.01. This is, again, not a bad error considering the fact that averaging over 2 superblocks provides 0.005 precision. If the whole range of values is desired for the B-Burst, further restrictions should be imposed upon e. Another alternative is to compute a correction table for the desired result, so that for cer- tain values of the B-Burst a certain correction is added. 21 2.4 Output Counter The function of the output counter is to count the pulses coming out of the arithmetic unit in a certain amount of time. These pulses may come in an uncompacted form, e.g., the adder output, and the counter does the averaging of the result so that a constant Burst repre- senting the averages of the sum, difference, product or quotient can be sent to the actual output. In the case of multiplication, where two 10 percent precision Bursts are multiplied and a I percent precision result is generated, the amount of time that is necessary to count all possible pulses is exactly 100 clock periods. This time allows the accumulation of up to a maximum of 100 pulses which result from multiplication of the maximum Bursts. The output of 1 percent precision Bursts requires a period of a superblock, too. Therefore, the output counter can be built of a counter of maximum content 100, which counts the pulses during a period of a superblock and then produces an output during the next superblock. Ob- viously, such a counter will be busy producing the output eyery second superblock and, consequently, no counting can be done on the new Bursts that come in in that superblock. To get around this problem, a second counter can be used which computes the next result when the first counter produces the last output; and then the functions are switched so that the first counter computes the next result and the second counter produces the output, and so on. In this manner, the output stream is continuously filled with output Bursts and no gaps occur. Additionally, no input Bursts are lost. 22 Since scaled division is performed in BURSTCALC, i.e., A/lOB, the range of magnitudes of the quotients is 0.01 to 1.0, and the preci- sion necessary is, again, 1 percent precision for both input and output of the output counter. Accordingly, the same counter that was used for multiplication can be used for division. It was previously shown that in addition and subtraction the basic period of computation was 2 blocks. Therefore, the necessary counter for these operations should be a counter of 20. However, a spe- cial counter of 20 would complicate the output system both in chip number and logic complexity. In order to keep these two factors as low as pos- sible, the same output counter mentioned above is used in addition and subtraction, too. Obviously, this counter averages over 10 blocks, or 5 times the necessary period of 2 blocks, and better averaging is achieved for these operations. On the other hand, the ON-LINE feature of the adder and the subtractor is affected slightly. The output counter should be designed in such a manner that the production of the Burst output, after the computation is over, is very easy. The solution is a 10-bit shift register shifting ones according to the count pulses and using the tenth bit to indicate overflow; this overflow then causes shifting of ones in a second shift register. After the computation period is over, the first shift register contains the unit count and the second contains the tens count. Since all the ones in the tens shift register are adjacent, the production of Bursts from its contents is as easy as shifting out its contents. At this point it should be emphasized that the actual output contains information with 1 percent precision at most so that we need a 23 period of at least a superblock. However, the output can be made con- stant over a superblock and change only at intervals of superblocks so that a 1 percent precision is accomplished by averaging over 10 super- blocks. This, clearly, is not a faster way, but it helps in decreasing the hardware complexity of the output counter, as will be shown immed- iately. Additionally, the precision of the result is always better than 10 percent, as shown in Figure 2.7. If the 1 percent precision Bursts are produced during a super- block, the output should represent the contents of both the units and the tens counters of the output counter. For example, a result of 0.23, or 2 tens and 3 units, requires the transmission of the sequence: 3,3,3,2, 2,2,2,2,2,2; that is, units times the tens digit plus one and then ten minus units times the tens digit. In a case of a round result, say 30, or 0.30, the output should be simply 10 threes. The hardware implemen- tation of the above word description seems to be relatively complicated. In the second method, where the output is constant over a superblock, the output consists of the contents of the tens counters only and the units counter is common to both tens counters. The output is done by simply taking the contents of the tens counter 10 times: This system is much simpler! The block diagram of the output counter is shown in Figure 2.8. The units counter serves both tens counters. The output consists of the contents of the tens counters only as mentioned above. However, any re- mainder in the units counter is added later by the other counter so that these units are not lost. CK200 is a signal with a period of 200 clock a: o 24 CSJ 00 CM r*v CM i£> CSi LO CO C\ICMCMrOC\ICMCOC\JC\jn CSJCMCMOOCMCMCOCVJCMO-) c\JC\Jc\joocMC\iroc\jc\ioo c\jcMc\jcoc\jc\jcoc\jc\in CMCMC\JCOCMC\JCOC\JC\|00 «a c «a Q. in T3 o 3 Q. 3 o I s- (U <;r CM CMCMCMCOCMCMCOCMCMrO o o CO CO CM 00 U 1 — CO r^ J3 S- 0) Q- • • 3 :^ 00 CO CM (O _i CO CD t— 1 U- • UJ 1— cC CI5 00 ZD ■ Q. +-> O 00 cvj Ol s- Z3 on 26 periods and a duty cycle of 50 percent, which switches the two tens counters between the computation mode and the output mode. The actual operations performed in these modes are shifting left and rotating right, respectively. That is, in the computation mode, the overflows from the units counter are used to shift ones left in the tens shift register. After CK200 causes switching to the output mode, the contents of the shift register are rotated right 10 times by the system clock and sent concurrently to the actual output. As a preparation for the next com- putation period, the tens counter is cleared during the tenth rotation. This is done by actually blocking the rotation path by the signals CK91 and CK92, which are low only during the last 10 clock periods of the re- spective output period of each tens counter. In the more complicated system that was described above, sepa- rate units counters should be used in each section, and each section should include a special mechanism which determines what Burst to generate and how many times to generate it during the output mode of the section. 27 3. MACHINE DESCRIPTION. 3 . 1 Front Panel The front panel contains two banana plugs for VCC and GND, the mode selection switches and their appropriate indicators, 11 input switches for each Burst representing the constant Bursts sign and mag- nitude, and finally two banana plugs for the input of two analog signals which may be encoded into variable Bursts. The display on the front panel includes 11 LEDs for the sign and the magnitude of the result and, also, two banana plugs for a DC averaged result to be displayed on an exterior meter. BURSTCALC should be operated on a single +5 V power supply with a 2.5 Amp capability. After switching the power on, an arithmetic oper- ation may be chosen by means of the mode selection push buttons: ADD, SUB, MUL or DIV. Four LEDs are used to indicate which mode was selected; they are located right above the respective push buttons. Although a clock connector exists on the front panel, no external clocking is neces- sary because the clock is internally generated. However, if a different clock frequency is desired, an external clock may be connected to the coaxial plug input. The internal clock should then be disabled. The Bursts inputs can be determined by the 11 switches assigned for each Burst. Each switch of the magnitude switches controls an ap- propriate time slot, e.g., Al controls the first time slot in A-Burst, A2 the second, etc. The sign of the Burst is determined by its respec- tive sign switch. The switches described provide constant Bursts to 28 BURSTCALC. However, if variable Bursts are desired, analog signals should be entered via the banana plugs and the appropriate input Burst selector switch should be flipped to the VAR position. This is des- cribed in more detail in Section 3.4. The selector switch is, actually, located on a PC board. After the mode has been selected and the appropriate Bursts inputs have been set to the desired values, the result can be read out on the 11 LEDs of the display. This display provides a crude 10 percent precision result with 0.1 indicated by the lowest LED illuminating, 0.2 by the lowest and the next to the lowest, etc. The eleventh LED pro- vides the sign of the result. If an exact, 1 percent precision, result is desired, it can be extracted by connecting a DC meter to the DC output banana plugs. The meter will perform the appropriate averaging of the voltage coming out in these plugs. This is described in Section 3.5.1. If the full-scale reading of the meter is adjusted to 1 V with a result of 1.0, the meter reading may give a 1 percent result for all the results between and 1.0 If it is desired to have the actual Burst output, the analog output selector switch should be flipped to the PULSE position. The Burst output may then be taken from the same banana plugs. The output selector switch is located on a PC board. 3.2 Timing Generator and Mode Selector The timing generator provides all the necessary clock signals to the machine. These include the symmetric main clock which is 29 internally generated; a dual phase system clock (Tl , T2) which is gen- erated from the main clock; CK2, CK20 and CK200 which are the clock Tl frequency divided by 2, 20, and 200, respectively; CKIO has a period of 10 Tls and is active only during clock periods 9 to 10 of each cycle. Finally, CK91 and CK92 have a period of 200 Tls and are active only during clock periods 90 to 100 and 190 to 200, respectively. The main clock frequency and duty cycle can be adjusted by means of the po- tentiometers provided or by the connection of an external clock on the front panel. The detailed diagram of the timing generator is shown in Figure 3.1 . Tl is the system clock which is generally used in shifting operations during the computation or the output of Bursts. It is cur- rently adjusted to 1 MHz and 50 percent duty cycle. T2 is the inverted version of Tl and is used in the generation of both input and output Bursts. CK2 and CK20 are used at the adder as described in Section 2.1, CK20 is also used in the subtractor (Section 2.2). CKIO is generally used in the machine in loading or clearing of registers. CK200 is used for the determination of modes of operation of the two parts of the output counter as was shown in Section 2.4. It should be noted that since all the operations performed in BURSTCALC are continuous, no complicated control circuitry is necessary, These operations include the arithmetic operations, the output genera- tion, the Burst input generation and the display of the result. Conse- quently, all the control signals for each part of the machine are com- pletely periodic and the timing generator reduces to a simple counting system, as shown in Figure 3.1. 30 o o CM u o o 1-^ o o K CJ -^ (\i (/> ^ X ^ >- o a o (O >- CO i A !f ! o 5 E E 0) .c u oo o fO t. c TT CO C7) o ♦ K- lO ^*^^ J TT A z o 31 The mode selector is used in the selection of the desired arithmetic operation. The detailed diagram in Figure 3.2 is self- explanatory. The out signals: ADD, SUB, MUL, DIV and MUL/DIV are used in their corresponding part of the arithmetic unit and in gating the pulses that go to the output counter. 3.3 Arithmetic Unit The various parts of the arithmetic units of BURSTCALC have been described in Chapter 2. The actual realization of those parts is not different from the diagrams shown. This includes the adder, the subtracter, the multiplier-divider, and the output counter. The only part that has not been described is the sign generator. A detailed scheme of the sign generator is shown in Figure 3.3. For multiplication or division (MUL/DIV) the output sign is the EXCLUSIVE- OR of the two input signs. When the ADDENA signal is active, enabling the adder, the output sign is exactly the sign of the A-Burst (SA). When the SUBENA signal is active, showing that the subtracter is enabled, the determination of the output sign depends on the relative magnitudes of the subtracted Bursts. Flipflop SOSUB is cleared or set at the be- ginning of each 20 clock periods by the SA and the CK20 signals (with the upgoing edge of the latter!) so that the initial sign is set to the sign of A. CK20 changes its state after 10 clock periods and releases the clear and the set of SOSUB. If, during the second 10 clock period, the INVERT SIGN signal appears, indicating that the B-Burst is greater than (or equal to) the A-Burst, it clocks into SOSUB the inverse of SA, as 32 o v. -I Z ^^>-wv (g) o <]- 3 > o o o < 3 CO m m \ ;.H^ (g) o<^ \ y-"^ ( w ) <<}- \ ?*-^^^^^-@-<} - < o a z o liJ E s- o ■M O 0} 'oj -a o CSJ (U S- 33 o s- cu c O) o CD •r— to CO CO O) i- 13 cn < OD CD Q OT V) 3 O tf) < A > a -i s o K 34 can be verified from Figure 3.3. Therefore, after each 20 clock periods are over, SOSUB contains the final output sign and this sign is loaded into the SO flipflop by CK20. The same edge of CK20 begins a new cycle of sign determination. SO is used for the actual sign of the result. Note that in multiplication/division and in addition the sign is loaded into SO by the same CK20, periodically, from the AND-OR network that selects the desired sign. 3.4 Input Burst Generators Each incoming Burst to the arithmetic unit is generated, both sign and magnitude, in its resepctive Burst generator. Since the two generators are identical, only the A-Burst generator is described. Every Burst generator includes two subgenerators: the con- stant Burst generator and the variable Burst generator. A switch is pro- vided to select the desired Burst. The constant Bursts are derived from the 11 switches on the front panel as described in Section 3.1. The variable Bursts are encoded from an analog voltage, which is fed to the banana plug on the front panel. A more detailed description follows. 3.4.1 Constant Burst Generator This generator is called constant Burst generator because the generated Bursts result from the position of switches and, obviously, switches cannot be switched fast enough for the machine to recognize the generated Bursts as variable Bursts. The diagram of the constant Burst generator is shown in Figure 3.4. 35 Tl> AlO r A9 A8 j: A7 A6 ^ A5 ^ A4 "■ X" A3 r A2 _r Al j: T2> A-SIGN ± D1-D6 TO GND. + 5 ft >1K •IK + 5 :iK •IK •IK •IK •IK •IK ►IK •IK + 5 ►IK LA SRIN CK 01-D6 07 08 SHIFT/ LOAD 74166 Q8 01 02 03 04 05 06 07 08 SRIN CK SHIFT/ LOAD 74166 08 CKIO V 7408 o A-BURST INPUT SELECTOR I "JCONST VAR FROM VARIABLE BURST GENERATOR > A-BURST OUT SA Figure 3.4 Constant Burst Generator Diagram 36 Tl is used to shift the Bursts out of the shift register, Every 10 clock periods (CKIO) a synchronous load signal loads the status of the switches into the shift register and then the contents of it are shifted out. In order to avoid timing problems, T2 is used to actually generate the Burst pulses, so that enough time has been provided for Q8 of the shift register to settle after the shifting or loading by Tl . 3.4.2 Variable Burst Generator The variable Burst generator is a generator which is more suit- able for the intended function of BURSTCALC; namely, calculations on Bursts which were encoded from various transducer outputs. This genera- tor provides variable Bursts to the arithmetic unit, so that the unit can be checked under more realistic conditions. The variable Burst generator is an exact duplicate of the well- known Burst Encoder, with the exception that it encodes only 10 different levels instead of 100 levels. A scheme of the variable Burst generator is shown in Figure 3.5. The analog signal voltage swing should be ad- justed so that it does not exceed the voltage swing of the staircase waveform which comes from the BSR. This adjustment and the staircase adjustments may be done by the two potentiometers provided. Some Burst Encoder waveforms are shown in Figure 3.6. In its current form the variable Burst generator cannot generate the sign of the Bursts and, therefore, the same switch that was used for the sign in the constant Burst generator is used here. 37 M gev en o -M s- q; E OJ C3 S- CQ OJ JD (O •r— i- fO CO (U S- CD 38 Ui o o o z UJ oc CD cn en z < o > i. 0) o u c 00 CO 3 39 It should be noted, at this point, that the main purpose of the variable Burst generator was to check the multiplier and the divi- der under the conditions of changing Bursts (especially changing B- Bursts!). Recall, from Section 2.3, that for the reduction of error in multiplication or division certain restrictions were set on the amount of change of the B-Burst. These restrictions can now be trans- lated into the restriction of the slope of the input analog signal which is used to derive the Burst inputs to the multiplier or to the divider. 3.5 Result Display The display provides a visual representation of the result coming out of BURSTCALC. The digital display provides a discrete display with a step size of 0.1. The analog display provides the DC average of the result and can be as accurate as the measuring device. The block diagram of the display system is shown in Figure 3.7. The sign display is a LED which indicates the state of the out- put sign flipflop SO in the sign generator. 3.5.1 Analog Display The analog display is provided by an averaging BSR which ac- cepts the Bursts and transforms them into a DC level. If the Bursts are constant, the DC level is constant, but if the Bursts represent 1 percent precision numbers, they may change periodically in magnitude and the DC level coming out of the BSR may change, too. This change may then be averaged by any voltmeter. 40 OUTPUT > BURSTS Tl > CK10> S0> 200 D CK BSR SUM OUT 10-BIT BSR 74164 Iz DISPLAY CK BUFFER 74174,74175 Iz 11 LED DRIVERS 7406 iz 11 LEDs DISPLAY SIGN AND MAGNITUDE -► + I ANALOG OUTPUT PLUGS -► — ' PULSE LZZTZTZ. J ANALOG OUTPUT SELECTOR Figure 3.7 Result Display Block Diagram 41 If it is desired to have the actual Bursts in the output, the analog output selector switch should be set to the PULSE position, so the output Bursts are directed to the output ports. The two potentiometers provide adjustments capabilities for the DC output voltage swing and for the Bursts amplitude. 3.5.2 Digital Display The digital display uses the fact that in each block of Bursts all the ones are grouped at the beginning of the block. Therefore, if the contents of the BSR, which is a shift register, are loaded into a buffer every 10 clock periods (by CKIO) all the ones appear at the right end of the buffer and can be easily displayed. Note that the contents of the BSR are the last ten Burst pulses in reverse format and that this pattern is shifted right ewery clock pulse, since the clock is applied constantly to the BSR (Tl). It should be noted that the ditigal display provides a 10 per- cent precision display, where the output Bursts may be of 1 percent precision, i.e., the Bursts may change from block to block. This causes flicker in those display LEDs that do not illuminate constantly. For example, if the result is 0.23 then both the first and the second LEDs come on with full intensity, but the third LED is only on 30 percent of the time. This may be a way to tell that the result is between 0.2 and 0.3, which is sufficient for a 10 percent precision result. 42 4. CONCLUSIONS BURSTCALC demonstrates that arithmetic operations on Bursts can be done by counting techniques and generation of averages of opera- tions instead of operations on averages of Bursts. Clearly, the prob- lems are in multiplication and division where averages of products or quotients are not equal to product or quotient of averages, and some errors arise if certain restrictions are not kept regarding the input Bursts. Additionally, it is felt that the signed numbers representation that was chosen may not be the best one and a different representation may simplify the circuitry. The clock frequency used is 1 MHz and so is the Burst pulses maximum frequency. This is imposed by the use of the 74' TTL family. The maximum frequency that was tested was 5 MHz. Pos- sible increase in speed of operation can be achieved by the use of ECL circuitry. As BSRs use semianalog processing, or averaging by analog means, they are faster than the sequential logic design presented here. However, the circuitry required is apparently more complex. The BSR adder with biased representation requires two 10- bit BSRs where the logic design requires: 4 ANDs, 2 NOTs and 1 OR only, when the sign and magni- tude representation is used. A BSR subtractor would use the same adder circuitry, but the logic subtractor uses two additional shift registers so that the complexity is the same. The logic multiplier-divider re- quires about 4 shift registers including the compare-select logic. A BSR design would require a special conversion system to convert the biased Bursts into sign and magnitude representation so that a simple I 43 multiplier can be used (see Reference 2). This might not be too com- plex but the division mechanism with BSRs would be the bottleneck, since it requires 4 BSRs. Finally, a reencoding system may be necessary to transform the result from sign and magnitude back to the biased repre- sentation. The output counter in the logic design is comparable in com- plexity and in speed to the BSR design Vernier Encoder so that they will not be considered in the comparison. It seems now that BSR design may be more complex than the logic design especially in view of the fact that the logic design does not have to use 10-bit shift registers. It is wery easy to replace all the 10-bit shift registers by 4-bit decade counters with an appropriate amount of logic gates in order to perform the same operations. This reduces con- siderably the number of flipflops in the system. The compare-select logic in the multiplier-divider would then become a little more complex but the overall complexity would stay around 50 flipflops. In the BSR design, using schemes as in Reference 2, a minimum of 4 BSRs, or 40 flipflops, are necessary for the adder-subtractor, multiplier and divi- der provided that the same BSRs are used for all the operations with ap- propriate analog switching. There still remains the output vernier en- coder for the encoding of the output Bursts which uses 2 BSRs and it may, also, be necessary to have conversion circuitry between the representa- tion methods, as described earlier. The number of flipflops is, there- fore, a minimum of 60. These figures show the superiority of the logic design. However, one important point that has not been considered is the fact that in BSR 44 design the arithmetic operations are performed ON-LINE and on already averaged Bursts whereas in the logic design problems arise, especially in the multiplier-divider, because no averaging of the input Bursts is provided. Therefore the BSR design still remains attractive for the implementation of a Burst arithmetic unit. A few words sho^uld be said about the weighted binary method; that is, conversion of the incoming Bursts into the usual two's complement binary form and performance of the arithmetic operations by well-known binary techniques. Since the Bursts in the logic design can accept the values of -1.0 to +1.0, the number of bits in the weighted binary ver- sion would be 5 bits. The logic circuits that may be necessary are: two 5-bit counters to convert the serial input Bursts into binary num- bers; two 5-bit registers to hold the operands during the calculation period and three more 5-bit shift registers which are necessary for multiplication and division. Finally, a 5-bit output counter is neces- sary which holds the result and, also, produces the Burst output. The operations can be performed ON-LINE with the input of Bursts into the input counters; then, unloading their contents into the buffer registers every 10 clock periods. In the next 10 clock periods, the computation is performed, after which the result is loaded into the output counter. The result, which is of 10 percent precision for a block of 10 slots, is rounded unless it is a multiple of 0.1, and is sent to the output in the following 10 clock periods. Obviously, this system has the same difficulties with multiplication and division as the logic design system. 45 Moreover, its lack of accuracy, due to rounding, may be cumulative if we average over long periods, so that the error may become too large. Con- sidering the circuit complexity, it can be established that the weighted binary design needs at least 40 flipflops for the counters and registers mentioned above; there should be added a 5-bit full adder and many gates for routing of data between registers; additionally, the multiply- divide control logic may not be negligible in complexity; finally, an excess of reencoding logic may be necessary in order to convert the re- sult back to Burst form. It seems therefore that the weighted binary design exceeds the (Burst) standard logic design in complexity; therefore, the latter, which uses counting techniques, should be preferred, as it is less complex and generates more accurate results in most cases. 46 LIST OF REFERENCES 1. Bracha, E., "Quarterly Progress Reports," Department of Computer Science, University of Illinois, Urbana, Illinois, January 1975, April 1975, July 1975. 2. Poppelbaum, W. J., Appendix I to "A Practicability Program in Stochastic Processing," called "Burst Processing," Department of Computer Science, University of Illinois, Urbana, Illinois, March 1974. 3. Poppelbaum, W. J., Computer Hardware Theory , Macmillan, New York, 1972. 4. Robertson, J. E., "Introduction to Digital Computer Arithmetic," Digital Computer Laboratory, University of Illinois, Urbana, Illinois, June 1964. BIBLIOGRAPHIC DATA SHEET 1. Report No. UIUCDCS-R-75-769 3. Kcc ipicnt's Accession N< 4. lit !<• .\nd Siihi ii li BURSTCALC (A BURST CALCulator) 5. Report Date October 1975 7. Aiuhor(s) Ehud Bracha 8. Performing Organization Kept. UIUCDCS-R-75-769 No. 9. I'lrloniiing Organizarion Name and Address Department of Computer Science University of Illinois at Urbana-Champaign Urbana, Illinois 61801 10. Froject/Tasic/Work Unit N. 11. C.ontract/Grant No. N000-14-75-C-0982 12. sponsoring Organization Name and Address Office of Naval Research 219 South Dearborn Street Chicago, Illinois 60604 13. lype ot Report & Period Covered Master's Thesis 14. 1 ■-, .siipplemenrary Notes 16. Abstra t s BURSTCALC is an arithmetic calculator which accepts inputs in Burst format and produces their sum, difference, product and quotient in Burst format, too. It uses simple counting techniques on the incoming Bursts in order to compute the desired arithmetic operation with low precision, so that relatively simple and low cost circuitry is used. However, higher precisions can be achieved by averaging the result over longer periods. 17. Key Words and Document Analysis. 17o. Descriptors Burst Processing Block Sign and Magnitude Representation Biased representation 17b. IJi III if iers /Open-Ended Terms 17c. C C)>ATI Field/Group t IR. \\ .iil.iliility Statement Release Unlimited 19. Security Class (This Report) UNCLA.SSIFIED 21. No. of [>age-. 52 20. Security Class (This Page UNCLASSIFIFD 22. Price FORM tgjIS-l'i (10-70) USCOMM-DC 4n329-r-'l *. \^ ■^'^-