LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN ■LSHsX cop- 2» CEKTRAt CRCUIAT'ON , BRACKS the library from whicft u stamp ed on or before the W«* B „,.,„•,„«„» ^KootfJE lost book. fee of $75.00 tor ^ reojons for dtodpW""'* «« tlon an ° s ass* — i-srS^sa SEP lb u We write new due date below When renewing by phone, writ u62 previous due date. Digitized by the Internet Archive in 2013 http://archive.org/details/educationalproje535este fj/yy UIUCDCS-P.72-535 ~ z^ EDUCATIONAL PROJECTS FOR A DIGITAL LOGIC LABORATORY By Thomas A. Estelita IH E LLBR A8Y QE me c r; IE 1972 July 1972 UNIVERSITY OF ILLINOIS ATUf ^CHWAIGN -• fp UIUCDCS-R-72-535 EDUCATIONAL PROJECTS FOR A DIGITAL LOGIC LABORATORY BY Thomas A. Estelita July 1972 Department of Computer Science University of Illinois at Urbana-Champaign Urbana, Illinois 6l801 *This work was supported in part by Contract No. AEC AT(ll-l) 1U69 and was submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science, August 1972. jZJi bh^ iii /U) •, 535 ~ ^ t f i PREFACE Educators hare long been aware of the time lag between the develop- ment of modern innovative techniques and their initial inclusion in undergraduate laboratory courses. To become a valuable teaching experience a laboratory program must be of valid current concern. Today 1 s student is not interested in yesterday* s challenges; he seeks involvement in current technology. A lecture can present the mathematical model, but a laboratory brings the model to life and lends meaning to the new found knowledge. This study attempts to fuse together the theoretical and practical aspects of a digital logic design course. Pertinent, working examples are detailed to illustrate the complexity to be experienced in a one or two semester undergraduate logic laboratory. These example experiments are presented in a multilevel program of laboratory exercises. The study concludes with ideas for additional experiments and further suggested design challenges. No a priori knowledge of electrical circuit design and analysis is assumed. The development of integrated circuit technology has made such knowledge unnecessary. The logic designer is thus freed to think at the system level as well as in the more familiar terms of gates, flip-flops, fanout, and circuit delays; he can manipulate these quantities without concern for the detailed circuit operation. The experiments presented within this study are typical of those required of the student. Relevance and practicality, besides design content, are the desirable properties chiefly responsible for their inclusion. Additionally, consideration has been made to the machine independence of each design. Although each experiment was designed and IV tested on the EXCEL logic laboratory in present use at the Department of Computer Science, University of Illinois, Urbana, these experiments could be implemented on any logic "kit" of similar complexity. A brief description of the EXCEL system, reinforced by a detailed examination in the appendix, is presented to explain its capabilities for comparison. At this point, the author would like to thank Dr. Michael Faiman, who provided most of the inspiration and considerable perspiration in making this study possible. Finally, I wish to thank my wife, Billie, who typed the complete study and patiently endured my many hours of absence during its preparation. TABLE OF CONTENTS CHAPTER PAGE 1. THE LOGIC LABORATORY, ITS GOALS AND CH ARACT ERISTICS. ... 1 2. INTRODUCTORY EXPERIMENTS 11* 3. INTERMEDIATE EXPERIMENTS 33 1*. THE TERM PROJECT 62 $. CONCLUSION 75 LIST OF REFERENCES 77 APPENDIX 79 1 CHAPTER 1 THE LOGIC LABORATORY, ITS GOALS AND CHARACTERISTICS 1.1 Introduction Instruction in logic design is considerably more effective if the student is given the opportunity to apply a "hands on" procedure to a working system. In addition, the learning motivation is enhanced by extreme gratification in a working practical logic system of one's own design. The hardware equipment for digital systems has, with the advent of recent technological innovations, become comparatively inexpensive. Hence, even the educator of moderate means can now provide a digital logic laboratory of sufficient complexity to allow students to explore the internal workings of a modern computer. A common approach to a logic design course is to teach concepts in digital design and then confront students with problems which might illustrate a particular point to be emphasized. The alphabet of problem solution is one of "gates," "flip-flops," simplification procedures and "timing diagrams," but the student may rarely see a logic module or clearly grasp its limitations. A logic laboratory bridges the gap be- tween material presented in lectures and the confrontations of reality. Almost everyone who has programmed a computer has at first worked out what he may have thought to be a workable solution to a problem, only to find that he may have overlooked an unforeseen circumstance when attempting an actual computer run. Likewise, one cannot impart sufficient confidence in a complicated logic design until it too has run to complete satis- faction. Historically, logic design grew up within the realm of Electrical Engineering (EE). A circuit designer would manipulate circuit elements to perform a logical function under certain current and voltage conditions. Considerable circuit duplication and miniaturization led at first to modularity and then to integrated circuit (IC) packaging. Standardizing these IC packages along logical function boundaries has in effect divorced the electrical circuit designer from the logic designer. The man at the design bench now manipulates IC*s or logic modules. Manufacturers advancing a new technology, which may provide greater speed or higher reliability, must conform to the accepted norms of logic function packaging or now face incompatibility. Hence, logic design can be presented early in an undergraduate study because no specific technology need be attributed to the derivation of the logic function. No specific technical knowledge is presupposed, other than the basic formalism of switching algebra. A properly designed logic course which also includes student exposure to a logic laboratory need not be limited to EE students but may be expanded to include anyone excited by the prospect of creating hardware that performs as designed. Just as a computer programmer need not understand the intricate details of a computer to make it function, but need only obey the rules dictated by its architect, so a logic designer need not concern himself with the inner workings of an IC, so long as he does not violate the circuit's limitations. It is this recent step-up in specialization that allows educators to introduce logic design courses at lower undergraduate levels and hence introduce relevant new topics. Today's student must be prepared to confront the challenge of the future and not be kept busy with yesterday's requirements. 3 The student making the transition to graduate school has the op- portunity to develop research abilities in a logic laboratory course. Success with relatively simple projects develops confidence and initiative to pursue more complex topics. A logic design course which includes a laboratory as part of the curriculum, helps to span the void of undergraduate and graduate research ability and also satisfies the need of students to gain a foothold in today's technology. Another goal of a laboratory course is to develop a personal relationship between students and faculty. Very often a professor is called upon to recommend a student for a program without really knowing the student, or his specific abilities. An informal laboratory situation provides the means for an exchange which may not otherwise present itself in a sterile lecture-only presentation. The student who is allowed to pursue to its conclusion a particular project that interests him finds motivation to seek-out and understand the earlier concepts that he may have at first valued of little importance, The resourceful student is rewarded by the satisfaction of creating something perhaps for the first time. Other students derive satisfaction of accomplishment. All become benefactors of a profitable learning experience . 1.2 Properties of a Functional Digital Design Laboratory Course Introductory experiments in logic design may be used to verify pertinent lecture material, but in addition should possess limited practical value. These experiments should be necessarily short in h duration and in complexity. The transition to intermediate experiments should be made early in the course. The student who has not yet mastered the basics will find incentive enough to go back and review them properly; especially when he finds that he spends an inordinate amount of time rediscovering well known principles. As experiments become more complex, the student may find that he may have awakened an interest in a particular project; at this point he should be allowed to pursue the idea to his own satisfaction. The argument for a multilevel laboratory course is well founded. Properly implemented, the laboratory course provides a suitable oppor- tunity for realistic design experience in digital computer engineering. The primary level provides the broad based practical design experience necessary to continue. Here the apprentice learns the relationship between the mathematical model and its physical realization. In the secondary stages, the student learns detailed logic design and con- struction. In the advanced level, new design techniques peculiar to a given problem set evolve. Those students who do well can be encouraged to further pursue untried investigations in more advanced courses or graduate school. Hence, a multistage laboratory program can evolve covering all the details of digital and computer system design and in addition inspire the curious to continue. Within each stage of development, there exists a further gradu- ation of experimental difficulty. The student with prior experience, or the exceedingly bright student, can then seek the level of experience that presents the greatest challenge. 5 In the one -semester logic laboratory course at least three levels of a laboratory program have been identified: introductory, intermediate, and project. The introductory level introduces the student to the equipment. In an early part of this level the equipment limitations should be strongly stressed. Equipment abuse is perhaps the greatest cause of hardware failures. By first developing good laboratory procedures and requiring religious observance of logic module interconnection rules, a substantial amount of equipment can be saved for further use. Small electronic modules and integrated circuits are most unforgiving of even minor infractions of the rules. Also in the introductory stage the student discovers that theoretical material has a working practical value. The student should be required to work out on paper a feasible solution to the problem before coming to the laboratory. His laboratory work then verifies the theoretical material or identifies why the paper solution failed. Once a physical realization is achieved, encouragement can be given for improving the design and testing the circuit. A minimum of "make work" type experiments should be encountered. To confront a student with monotonous drudgery at an early stage soon breeds discouragement and frustration at a point where the excitement of discovery could be the greatest. Finally, the introductory exposure provides an experience in design feasibility. The student not only discovers what the hardware can do, but also what it cannot do. This lesson is most practical as it can save wasted effort in the future. The intermediate stage of development is an exploration of initial interests of practical value. The full impact of logic design is observed first hand as the student creates, models and analyzes increasingly more complex circuits. Technology becomes alive before him. Solutions to some problems pose questions to be explored and the adventure of discovery spurs further endeavors. Having developed some working background in analysis and synthesis, the student then generates alternative approaches to viable solutions. The flavor of an engineering program in design development whets interest in challenging more complex topics. At first the problem is defined. Solutions are then proposed and analyzed. Having decided on a method of approach, the student creates a working model. The model is then analyzed in light of its alternatives and practical value. Having decided on a realization, the final presentation is made, along with a discussion on recommended further improvements. Intermediate projects should be of a week or two in length. Hence, ample time must be allotted to explore a question to its final solution. The final phase of a logic laboratory should be devoted to a project of considerable depth and width. Perhaps as much as one-third to one -half of the course should be directed to this significant end. The project should be marked by significant steps in the program. At first a possible logic machine is proposed. Additional specifications are gathered and a statement is made. Next an interpretation is proposed and examined for inclusion in the solution set. Essential parts of the problem are then identified, maps of the problem statement are made and the essential parts are labeled. The next step is selecting the alphabet 7 for the problem. What choice of modules is to be made? Should one choose expensive, innovative techniques or use standard familiar devices? The final stage is implementation of the device. Drawings, sketches and models are proposed as solutions. The final design is then frozen, physically completed and presented. This decision to freeze a design and go to production is an essential part of the process that simulates in detail a real engineering program. Final evaluation of a design should be based on realistic standards. Minimization techniques should be stressed early in the course. However, it must also be clearly demonstrated that minimality is capable of many interpretations in the context of logic design. In some instances a minimal gate design is less desirable than a minimal IC design. In another case, the design with the least wire interconnections may be desired. Minimal cost may yield to increased speed of performance. Realistically, a design's worth is based only on its survival in a competitive environment. 1.3 Hardware Realization of a Logic Laboratory Of necessity a logic laboratory course is centered around the hardware made available to the student. Certain features of the hardware can be explored for maximum efficiency and educational impact. Present day integrated circuits provide logic function modules that are low in cost, small in size and low in power consumption. A logic laboratory should then take full advantage of each of these features to present to the student a small package that is of minimal cost. 8 The logic laboratory should provide access to an efficient mix of basic building blocks and more complex modules. Just having a numerous array of basic logic modules is not enough. The argument for providing complex modules is one that is well founded. First, a more complex module may provide a self-contained function that would normally ex- haust the supply of basic building blocks. Second, the more complex module simplifies the circuit and reduces the chance of design error. Third, the self-contained complex module partitions the design problem to one of interconnecting large modules. Fourth, design becomes more flexible and hence easier to change. Fifth, modules provide ease of troubleshooting and maintenance. Finally, the module is inherently cheaper since it saves design time each time it is utilized. A logic designer faces problems similar to those of a computer programmer. The programmer discovers that certain parts of a program interact in a limited manner with the rest of the program. He can then isolate these parts into modules that he calls subroutines or procedures. In this manner he accomplishes flexibility in his program; maintenance and debugging become easier. Every programmer makes substantial use of the subroutine library made available to him. By their use he can save his time and perhaps avail himself of routines of better efficiency then he himself may be capable of producing. In a like manner, a logic designer has a catalog of available logic modules at his side at all times. A pertinent part of the design process is to avoid duplicate effort and make maximum use of existing material. Let us now consider the various logic configuration to be provided to the student. One generally finds a myriad of abbreviations and confusing claims. There is resistor transistor logic (RTL), direct coupled transistor logic (DCTL), diode logic (DL), diode-transistor logic (DTL), emitter coupled logic (ECL), transistor-transistor logic (TTL) and many more. TTL seems to be a logical choice at the time of this writing because of its low cost, high speed, good noise immunity and established popularity. Any immediate developments beyond TTL would assuredly be TTL compatible, so that future expansion would be relatively inexpensive. Considerable thought should be given to the method of module interconnections and packaging. -An extensive study and evaluation of the various methods is presented by the Cosine Committee f s Task Force on Digital Systems Laboratories Report, entitled "Digital Systems Laboratory Courses and Laboratory Developments" I 3~| • A design consideration might also consider room for expansion beyond the present desired capability. Besides providing for unit interconnections and common power requirements, a logic laboratory might leave room for future additions. Due to rapid technological changes, a laboratory facility could soon become obsolete and consequently of diminished value if no consideration were given to continued updating. Another consideration of no little consequence is the hardware failure question. Even under normal use, IC's will eventually fail, interconnection wires will break, lamps will expire and switches will malfunction. Hence, thought must be given to the ease of maintenance and availability of replacement parts. 10 1.U EXCEL Logic Laboratory The EXCEL system £6] has all the desirable properties of an efficient, well designed logic laboratory. It is the system used to illustrate the experiments used in the remainder of this paper, and a short description of this system is therefore warranted. EXCEL is a modular system developed and manufactured at the Department of Computer Science of the University of Illinois, Urbana, under the design of Dr. Michael Fairaan. EXCEL is an acronym for experiments in computer electronics and logic. The EXCEL system is basically a box of electronic logic networks and modular components with their input and output connections handily exposed to the experimenter. Encased within the box (Figure 1.1^.1) is a well regulated, fuse protected, source supplying the power to drive the components. The logic integrated circuits are mounted on plug-in fixed patching units or cards (Figure 1.1*. 2), which connect the integrated circuit by means of printed circuit rails to identifiable sockets along a top plate. Up to sixteen cards may be plugged into the open top box. Interconnection is achieved by insertion of a length of 22-gauge wire into the tie pinsj no special connectors are required. The TTL logic family is used exclusively because it provides a variety of logic styles utilizing a single power supply and for the reasons already stated. The logic box has grounding sockets on the exterior to allow experiments to exceed the capability of a single box. Additional space is provided within the box for another power supply so that future experiments involving analog circuits can be conducted. 11 FIGURE 1.U.1 EXCEL CARD BOX 12 25 I W CO cvi m a ON^K 13 At the time of writing, the EXCEL system comprises eleven different card types. These provide various source and display features, a reasonably efficient mix of small scale IG's (SSI) and enough medium scale (MSI) modules to implement a vide variety of designs. One of the cards (KLUGE) is a universal type to allow the inclusion of special purpose circuitry. The reader will find detailed descriptions concerning the circuits in the appendix. The experiments detailed in this paper are for the most part in- dependent. Implementation on the EXCEL system only dictated the clocks to be used and the type of input/output. With little or no modification, these circuits could be readily implemented on other logic laboratory equipment. Ill CHAPTER 2 INTRODUCTORY EXPERIMENTS 2.1 Basic Digital Logic Networks The design of logic networks is conventionally divided between two fields of concern: combinatorial and sequential design. This natural division occurs because each field has a characteristic approach to its solution. The combinatorial problem is solved by- means of truth tables and Karnaugh maps or equivalent techniques; the sequential problem by state diagrams and flow tables. Each of these processes should be thoroughly explored in the early stage of a laboratory experience. This will prevent wasted effort in subsequent levels. The first laboratory period should be a cautious introduction to the hardware. Besides the first onslaught of caveats and stern warnings, the student is confronted with strange devices which he must learn to use. The language he learns is that of switching algebra. A high voltage (H) is "true" and a low voltage (L) is "false," if one uses positive logic. An additional meaning is to translate the H as a binary one (1) and the L as a binary zero (0). A logic element interprets its inputs as either H or L and acts upon this information in a predesigned manner. The experiments contained in this study use positive logic where "true," "high" and "one" are used synonomously. The ability to distinguish between the two signal levels is a basic measuring technique and should be well understood by the student. Additional lessons of fanin and fanout might also be presented; also this lesson should be repeated later in the course as more complicated circuits occur. 15 Not all of the available logic elements need be presented In the introductory stages. Logic modules capable of a unique function can be presented as the need arises. In addition, an experiment designed to duplicate the function of a module might be presented as a prelude to its release. The student then learns the many benefits to be gained by modularity. 2.2 "Voting Machine" The beginning student at first must gain an appreciation for the many-variable combinatorial problems one so often encounters in logic design. A logical approach to the start of a laboratory course then might be to reduce a word description of what is required of a combinatorial circuit and design a machine which will perform the operation described. The solution should be evolved in light of cost and delay factors as well as logic element availability. PROBLEM ; Four judges are empaneled on a city zoning board. Each judge has a switch that originates an H or L signal as the judge votes yes or no, respectively, on the question before the board. The voting machine to be designed will light a lamp indicating passage of the measure on a majority yes vote upon consideration of the signals on the four wires to the switches. DISCUSSION : Let us at first assign names to the variables. If each of the inputs to the machine are called A, B, C, D, then the output function f(A,B, C,D) will be true when all four inputs are true or any three of the inputs are true. We can write a switching function as: f(A,B,C,D) = ABCD v ABCD v ABCD v ABCD v ABCD 16 To implement this non-minimal expression would take two levels of NAND gates using a five-input NAND and five four-input NANDs. Let us proceed to a reduction procedure and plot the terms of the function on a Karnaugh map, Figure 2.2.1. We find that the function reduces to: f(A,B,C,D) - ABC v ABD v ACD v BCD. A two level NAND realization of this circuit requires four three- input NANDs and one four-input NAND. An alternate method might be to consider the product-of-sum solution or: f(A,B,C,D) = TTM(0,1,2,3,U,5,6,8, 9,10,12). A similar reduction on this form produces: f(A,B,C,D) = (A v B)(A v C)(A v D)(B v C)(B v D)(C v D). A two level NOR realization of f(A,B,C,D) requires six two-input NOR's and one six-input NOR. SOLUTION : For minimum delay we shall decide on a two-level realization of the function. On the basis of minimal gates the sum-of -products form is the cheaper and can be readily implemented. The product-of- sum form requires an additional gate; also the number of internal wire segments are two more than the sum-of -product solution. Also, we find that six-input NOR's are not very common. Hence, the sum-of -pro duct solution is preferred for good design reasons. It is illustrated in Figure 2.2.2. As an extension of this problem, the student might consider a machine with three lamps: one to indicate each of the situations of "passage," "rejection" and "tied vote." 17 C A i — \ A 12 8 1 5 cr 13 9 3 7 15 II a CO i) 2 6 J 14 10 B D FIGURE 2.2.1 KARNAUGH MAP A B C A B D A C D D fm.b.co; FIGURE 2.2.2 "VOTING MACHINE" 18 2.3 "Wolf and Goat" PROBLjM: A farmer has liired a rather dull farmhand to protect his cattle feed and lone goat. The farmhand Is to signal an alarm if a "dangerous situation 11 exists. A dangerous situation exists if the barn door is open and the goat is nearby, so as to get to the cattle feed. Also, to complicate matters, a hungry wolf lurks nearby such that another dangerous situation exists if both the goat and the wolf are in sight. To aid the farmhand, you are to design a device which has three switches: one each for "wolf in sight," "goat nearby" and "barn door open." The hired hand will merely press the switches as to what he sees. A dangerous situation should cause an output from the device to be used as an alarm. You may assume that the wolf does not eat cattle feed. DISCUSSION : Let us make the following assignments to the variables of the problem: W * "Hungry wolf lurking nearby" G » "Goat in sight" B » "Barn door open" A » "Dangerous situation - sound alarm" A statement of the problem's truth is: A «= BGW v GWB v BGW A reduction of implicants yields: A - GB v GW - G(B v W) SOLUTION : A realization of the above function can be directly implemented using two NOR gates and is shown in Figure 2.3.1. A 19 SO O so SI D 5/ W o^3> W2 o 52 FIGURE 2.3.1 "WOLF AMD QOAT" Yl X 2 X 3 5d^ 5^ ' Y 2 Y 3 FIGURE 2.i*.1 "GRAY CODE CONVERTER" 20 significant reduction in complexity of simple problems such as this, is realized when one has available complemented as well as uncomplemented inputs . 2.k "Gray Code Converter" PROBLEM: A number code in which adjacent numbers differ in only one binary position is called a cyclic code; a particular form of a cyclic code is the 3-bit version shown below with its decimal and binary equivalent. BINARY (Y 1 ,Y 2 ,Y 3 ) 1 1 1 1 1 1 1 1 1 1 1 1 Design a circuit which will convert the Gray code (X..,X 2 ,X.J into its binary (Y ,Y 2 ,Y ) equivalent. DISCUSSION ; The first concern is to represent the binary output in terms of the Gray code input. By inspection we immediately note that I, -X, and the converter for this digit is a single wire connecting a switch representing the X,. input to a lamp representing the Y- output. Con- sidering Ypj we see that: ■L/j * A^A/jA-j V A. A/jA^ V A^Az-jA^ V A. AqA ^ which reduces to: Y 2 = X..X 2 v X 1 X 2 « X.,0 X 2 GRAY CODE (X.,X 2 ,X ) DECIMAL 1 1 1 1 2 1 3 1 1 k 1 1 1 $ 1 1 6 1 7 21 A similar enumeration and reduction of the terms of Y, yields: Y 3 - X 1 ©X 2 ©X 3 - Y 9 ©X, SOLUTION : Figure 2.U.1 shows how two EXCLUSIVB-OR gates can be wired to realize the desired converter. Circuits of this type can be extended very cheaply, since the logic to form a three-bit converter is employed in a four-bit converter and that of a four-bit converter used to make a five- bit converter, etc. The general relationship between stages is: n+1 n v n+1 However, unequal circuit delays necessitate using these outputs only after the maximum delay has elapsed. This delay could be significant in, say, a twenty-bit converter. An alternate solution might take this consideration to task. 2.^ "Switch Decoder" PROBLEM : Let four switches SO - S3 represent a binary integer in the range 0-1$ with SO as the most significant bit. Thus, SO S1 S2 S3 represents the number 13. Design a decoder that will light one of nine lamps corresponding to the switch setting of binary 1-9. A switch setting of lights no lamps and switch settings 10 - 1J? will light lamps numbered 8 and 9. DISCUSSION : The first seven statements to light the corresponding lamps may be written: 22 L1 » SO ST S2 S3 L2 = SO Si" S2 S3 L3 - SO Si" S2 S3 Lli = SO S1 S2 S3 l£ - SO S1 S2 S3 L6 = SO S1 S2 S3 L7 » SO S1 S2 S3 Reductions on the statements of lamp 8 and lamp 9 results as follows: L8 - SO (S1 v S2 v S3) L9 - SO (S1 v S2 v S3) Figure 2.£.1 shows a minimal gate design of the decoder. This solution involves forming the intermediate variables X, Y, P, Q, R, and S. NOR combinations of the intermediate variables produce the logic necessary to light lamps 1 - 7 (L1 - L7). A four gate circuit is also presented to light L8 and L9. The total design involves eleven two-input NOR gates and six two -input NAND gates; a total of seventeen gates. An implementa- tion on the EXCEL system would require at least three NAND-NOR cards. An alternate design is presented in Figure 2. £.2. This design uses eleven NAND gates and seven NOR gates or a total of eighteen gates, one more than the previous circuit. However, in terms of logic laboratory cards, this later design, because of its lesser use of NOR's, requires one less EXCEL card. In terms of IC's, the first solution would take two quad two-input NAND chips and three quad two-input NOR chips, a total of five IC's. The second solution involves the use of three quad two-input NAND chips and two quad two-input NOR chips also for a total of five IC's. All EXCEL NOR gates have two inputs. 23 X' S- r- X- R- Y- 0- x- 0- P- X- p- D~ LI L2 L3 -L4 L5 L6 L7 S * r> t> L8 L9 FIGURE 2.5.1 MINIMAL GATE DESIGN OF DECODER 2U s, s 2 s, 7 '2 S3 S3 r> r> ^►P ^0 -►/? c^ r ^ -►1/ W P u T- O- U- R- T - R - U S - T - S U £> u +»L2 I> L4 +-L5 *»L6 T>~^ L7 p w +*LB L9 FIGURE 2.$.2 MINIMAL EXCEL MODULE OF DECODER 2$ SOLUTION ; Either circuit presented plus a host more are likely- candidates for inclusion in the solution set. The point is that a minimal gate design is not always the desired solution. In this case a design involving one more gate reduced the number of modules involved. This may not be the case in another logic laboratory where the IC* s are clustered differently. Artificial criteria, such as the one just seen, are constantly encountered by the practicing logic designer. His company may have an over-supply of a particular logic module and hence the best design might be one using many of these modules. In another instance, use of that same module might be an unwarranted expense. 2.6 "Message Gap Detector" Sequential design calls into focus the flip-flop (FF). There are many varieties of this device, the most versatile being the JK. A logic laboratory could include a variety of types but, because of cost con- siderations, is more likely to contain many JK's from which the other types may be derived. A pair of inverting gates can become a simple flip-flop. In fact, every flip-flop type can be simulated using inverting gates and this makes available many early sequential design problems for the student. Subsequent experiments should be directed toward designs using the flip-flop as a packaged entity. The type available on the EXCEL system, is a garden variety, master-slave, threshold triggered, clocked, JK flip-flop (see appendix), and is the one used in some of the subsequent design descriptions. 26 PROBLEM ; A printer receives information from a data buffer via three wires: one line, zero line and clock * When the clock is H, the one line is H and the zero line is L to transmit a one, or the one line is L and the zero line is H to transmit a zero. Signals on the one and zero lines are constrained to change only when the clock is L. The presence of a message gap is indicated by both one and zero lines being Lj these lines may never be H at the same time. Design a circuit to provide an enable signal to the printer to indicate the presence or absence of a message. A typical timing sequence is shown in Figure 2.6.1 • DISCUSSION ; What is evidently needed here is a flip-flop which may be changed only when the clock is H. Provided either data line is H, the flip-flop should be (say) reset, and only when both data lines are L should it be set. SOLU TION ; Figure 2.6.2 shows a simple solution, in which the appropriate data condition is generated by a NOR gate and is gated into a NAND latch by the H level of the clock signal. In the EXCEL system, this is readily implemented using part of a single NAND-NOR card. 2.7 "Oscillator Switch" PROBLEM : Design a circuit which will gate the output of an oscillator. As the gate signal goes to H, the oscillations appearing at the input appear in synchonization with those at the output of the circuit. Additionally, shortened pulses are not allowed at the output. DISCUSSION ; A first attempt toward a solution might be to use a single NAND gate as the required circuit. However, a second consideration H L. clock H one line H L. H zero line printer enable \ 27 r\ FIGURE 2.6.1 MESSAGE GAP DETECTOR TIMING DIAGRAM BUFFER one zero clock ■^ PRINTER enable r> 3> FIGURE 2.6.2 "MESSAGE GAP DETECTOR" 28 quickly reveals that such a circuit does not satisfy the condition that shortened pulses are not allowed. Since the gate may go to H when the oscillator is already H, we need to note this condition and be ready for the next transition. Also if the gate goes to L when the output is H, then we need to shut off the oscillator on the next cycle. A flip-flop is employed to "remember" these conditions. SOLUTION : Let us attempt to gate the oscillator using a JK flip-flop. Let Q be the output of the circuit. Figure 2.7.1 shows how the flip-flop must act upon the inputs of the oscillator and gate. As a first attempt we might tie the oscillator input to the C input and the gate signal to the J input as in Figure 2.7.2. These signals are consistent with the JK functions. However, when the gate is H, this circuit will divide the input frequency by two and fail the first design requirement. An analysis of the input and output frequency waveforms of the circuit of Figure 2.7.2, will show that if we reset the flip-flop when both the oscillator and Q are H, then we will meet all design criteria. This design is shown in Figure 2.7.3, and involves an additional gate to provide an L at the overriding R (reset) of the flip-flop. 2.8 "Traffic-Light Controller" There are many instances where the design of a sequential circuit can be simplified by using cross-coupled inverting gates instead of the flip-flop module. The following problem illustrates this observation. 29 Q' gate osc J K L L L L X L L H L X H H L H X L H H X H "X"= DO NT CARE FIGURE 2.7.1 JK INPUTS gate osc "H" *■ *■ J c K osc gote u rLnsunn i FIGURE 2.7.2 FIRST ATTEMPT OSC _ruTJi_^jn_n_njT gate O rum FIGURE 2.7.3 "OSCILLATOR SWITCH" 30 PROBLEM : The traffic lights at the intersection of Main and Cross streets are to be controlled in the following manner: 1 . If traffic is present on both streets, the Main light is green during odd-numbered minutes and the Cross light is green during even- numbered minutes. 2. If traffic is present on one street only, the light for that street remains green. 3. If there is no traffic present, the light that was last green remains green. ii. If an emergency vehicle approaches on either street, both lights are switched to red. (After the emergency vehicle has passed, if there is no other traffic present, it is immaterial which light is green.) Design the necessary control system, using switches to simulate the inputs, and lamps for the outputs. DISCUSSION : Let us designate the inputs to the controller as: OD - "odd minute" EV = "emergency vehicle approaching" TC = "traffic on Cross Street" TM = "traffic on Main Street" VI ere it not for item 3, above, this would be a combinatorial problem. Figure 2.8.1 shows maps for the conditions "Main light red" and "Cross light red." X denotes a memory state corresponding to item 3» Since both lights are to be red for EV = 1, this suggests using a cross- coupled NAND flip-flop, with EV applied as an input to both halves. In addition, the flip-flop must be set (Main red) on the condition S = TC (OD v TM) 31 EV\ re X / 1 X / 1 1 1 1 1 1 1 1 TM main light red OD EV\ TC X I O O X I / O I I I I I I i I )0D TM cross light red FIGURE 2.8.1 FUNCTION MAPS GREEN MAIN *~RED ^RED CROSS GREEN FIGURE 2.8.2 TRAFFIC LIGHT CONTROLLER 32 and reset with R - TM (OD v TO) SOLUTION ; An implementation is shown in Figure 2.8.2. This solution has interpreted item 2, above, to mean that, when traffic approaches on one street only, the lights turn green for the traffic regardless of the state of the minute timer. In practice, this would pose the safety hazard of causing the lights, under certain circumstances, to change rapidly from red to green and back again. It is a straightforward extension of the problem to ensure that the lights can change no more frequently than once a minute. 33 CHAPTER 3 INTERMEDIATE EXPERIMENTS The division between simple introductory experiments and intermediate types is not well defined. To some extent the distinction is in the amount of hardware required or the time spent on the experiment. These measures are sometimes irrelevant to the complexity of design. However, the intermediate stage is signaled by a certain amount of design maturity on the part of the student. This significance allows us to be less specific in the statement of the problem; it is left to the ingenuity of the student to define the parameters in order to comply with an inherent design restriction, as the situation exists in the real world. This broad tolerance of design has a significant impact upon the designs presented here as examples. A circuit presented as a solution enjoys less uniqueness among alternatives. To this end, let us abandon the problem-discussion-solution sequence used in the previous chapter. Instead, let us present specifications that define the boundaries of the solution set. Next an approach to an implementation will be discussed under considerations . Lastly the various factors are gathered under impl ement at ion -which might also include suggested extensions, plus the description of a machine that meets the required specifications. 3.1 "Reaction Timer" Counters are used in a wide variety of digital instruments and digital computers. Binary counting can be achieved by chaining 3li toggle flip-flops in sequence. Each member of the chain divides its input pulse count by two. Hence, a modulo 2 counter contains n flip-flops. Except in special cases, however, it is rarely necessary for the designer to build his own counter from individual flip-flops. A variety of counters is available in IC packages, of which the 7li193 and 7M63 circuits, included in the EXCEL laboratory, are typical. The first few experiments in this chapter are samples of the variety using an event counter as their basis. SPECIFICATIONS : Car drivers should have fast reaction times, certainly of less than a second. It is desired to build a reaction timer that can measure an interval up to about 0.8 second to the nearest 0.01 second and display the result as two binary coded decimal (BCD) digits, repre- senting hundredths of a second, on lamps. There is also to be a "sluggard" lamp to indicate any reaction time longer than the maximum that can be measured. The timer itself should be a modulo 80 counter driven by a 100 Hz clock, so that each count represents 0.01 second. The counter's output, suitably decoded if necessary, drives seven lamps indicating a maximum of .79 second. Two switches control the system, which is to be in a clear state when both are off. The first switch is toggled to clear the counter. When the second switch is turned on, nothing outwardly happens for a few seconds (work out a scheme for achieving this), and then the counter starts to count up from zero. As soon as the person being tested sees the lamps beginning to flash, he is to turn off the second switch, which stops the counter, leaving the reaction time displayed. Only the sluggard light should be on if the reaction time is greater than the maximum. 35 DISCUSSION ; Basically the design calls for a counter which starts counting automatically at some variable time after the second switch is turned on, and stops counting when it is turned off. The EXCEL system has a slow clock, CI (1 Hz), which could be used to left shift a H bit in a shift register. Detecting a H at the left end of the shift register could be used to start the counting process. This means that, in a four-bit shift register, the counter begins counting after three to four seconds from the GO signal. If the C1 clock pulse is not displayed, the counter start is entirely unpredictable by the person being tested. Many methods could be employed to achieve the above requirement. It is only necessary that the waiting period from the GO signal be at least a few seconds and certainly no more than ten seconds. The C2 clock may be assumed to oscillate at exactly 100 Hz. Then each pulse from this clock increments a two-digit counting chain, originally reset to zero and displaying its counting, in increments to 79. One then reads the lamps used in display after the counting is halted by switching the GO switch to off. If .80 second elapses before this switch is activated, a carry into the "8" position of the high order digit stops the counting. This signal also lights the "sluggard" lamp indicating a reaction time greater than the maximum to be measured by this device. IMPLEMENTATION : Figure 3.1.1 illustrates a reaction timer. In its quisescent state RESET and GO are both off (i.e. RESET = H and GO - H), and the counters are cleared to zero. Now as the GO switch is placed on (GO = H), GO becomes L. Since QD on the high-order counter had been reset to L, the output of the NOR gate becomes H which removes the clear (CL) input to the shift register, 7U1 9h» The clock (C1 = 1 Hz) now slowly shifts the SL input H, to the left until it appears at QA. The QA output ties 36 CL H L S L SI SO ck 74/94 oa CL GO C2 RESET L \ 1 rrri CKCL D C B A 74163 LD0 . QD OC OB OA 6 6 6 6 RESET H SECs/lOO n. CL LD DN 74193 UP OD OC OB QA I X X X o o o o sluggard SECs/lO FIGURE 3.1.1 "REACTION TIMER" 37 directly to the T and P enable inputs of the 7U163 counter which then im- mediately begins to count up upon each pulse appearing at clock (GK) input. After nine pulses have been counted, the NAND gate output becomes L and this signal in turn reloads a zero into the counter upon the next count. Therefore, this module is wired as a decimal counter indicating hundredths of seconds. Also each output is connected to lamps indicating BCD readout. Each reload occurs once per ten pulses and hence is used as the input to the next counter in the chain. This high order counter counts up to a maximum of eight if the GO switch has not been switched off in the meantime. When the maximum count is reached, the NOR gate output becomes L clearing the shift register which in turn disables the low-order counter. This same result is accomplished by the person being tested. He places the GO switch to off before the maximum count is reached; this switches the output of the NOR gate to L disabling the counting process. The counters are initiated again by toggle of the RESET switch. There are many experiments that are variations of this timer scheme. For example, a digital clock is simply a specialized counter, incrementing upon precision one-second pulses. A down counter could be designed for use in a ignition sequence for a rocket launch. A device could use a photocell's indication to compute the time lapse for a photographic process and hence preset an automatic counter. An industrial use might be to count objects on an assembly line as they pass a detector. The following experiment is yet another practical use of a counting circuit. 3.2 "Automobile Tachometer" SPECIFICATIONS ; Design a digital tachometer for use in today's most popular automobiles. This instrument must present a digital display 38 capable of reading hundreds of revolutions-per-rainute (HRPM) and display HRPM to two digit significance. The principle to be employed here is to count distributor pulses for a fixed time interval T. The value of the count at the end of T is then proportional to the average HRPM for that interval. If T is short enough and the sampling is frequent enough, an accurate indication can be obtained. Moreover, as will be shown, it is possible to choose T such that the final count is numerically equal to the desired HRPM value. CONSIDERATION : This interval can be derived from a T generator which, in turn, is driven by an accurate clock frequency. It would be the purpose of the T generator to vary the T interval according to N, such that an N-cylinder engine would generate pulses, which are to be counted and displayed, corresponding to a HRPM indication. Typical values of N might be U, 6, 8 and 12, such that the tachometer is usable on most automobile engines. Counting sparks during the interval T yields a number proportional to the RPM. In order to round the digital readout to the nearest HRPM, it is necessary to count in units of .£ HRPM (50 RPM). This can be accomplished by setting a toggle flip-flop to H in parallel with resetting the counter to zero count. The first pulse from the N-cylinder engine distributor that occurs resets the toggle, which precedes in series the counter, and hence counts immediately to "one" indicating that 100 RPM has occurred since the start of the T interval. Subsequent counts occur for every two distributor pulses. Therefore, the counter indicates, say, K HRPM for an actual HRPM of between K + .5 and K - .$, as is desired for rounding. 39 PRECISION CLOCK tO Hz O-i 6 7" GENERATOR h* 7" J. JL_ A TOGGLE SMOOTHED DISTRIBUTOR SIGNAL 6 DECADE COUNTER 4- BIT LATCH DECADE COUNTER 4- BIT LATCH DECODE S DISPLAY FIGURE 3.2.1 TACHOMETER BLOCK DIAGRAM Uo The block diagram of the above method is illustrated in Figure 3.2.1, The counter indicates up to two digital places of value for HRPM. For engine speeds in excess of 10,000 RPM an additional digit could be added to the chain. The four-bit latches capture the final count to be displayed at the end of the counting period and hence are also con- trolled by the T generator output. The relationship between the period T and the number of cylinders, N, can be determined as follows. In the standard four-cycle engine, half the cylinders fire each revolution of the engine. Hence, for a N-cylinder, N four-cycle engine, there are — sparks to the cylinders from the distributor. This corresponds to a period in terms of .5 HRPM of: T _ 2 revolutions 60 sec . 1000 ms 50 JJ sparks x min. sec. i.e. 2l|QQ ms N For the popular values of N, T becomes: N = h 6 8 12 cylinders T = 600 U00 300 200 ms. If we use a precision dock of T Q = 100 ms (frequency =10 Hz) then the T generator should produce pulses separated by 2T Q , 3T Q , U£ Q or 6T Q as appropriate. IMPLEMENTATION : Figure 3.2.2 details the general structure presented in the previous section. Let us first turn our attention to the structure of the T generator. As its heart is a 7ij.1 93 counter, wired as a frequency divider, that generates a negative going pulse at the carry (CI) output when all outputs are H and U1 C2 CK CL 74I63 QA QD r DISTRIBUTOR SIGNAL , DECADE CK CTR R !! V k A B C D 74 I 9 3 O UP CY LO I -< H ^C ULi A B C D SO • l 74I94 CK QA QBQC QO < DECADE R CTR CK J w V V A B C D 7 41 94 s0 QA QBQC Q3 t Y Y ,f OOOO X I HRPM J so o so

S2 Q K ~5~ FF2 C K SI SI A G2 ££ so s/ Tt S2 S2 S4 Ft EN TER I EN TER O CLEAR NORM SORT LOAD NORM CLEAR FIGURE 3.14.1 "SQUARE ROOTER" 52 sums the output of the shift register, the counter and FF2. FF2 initially adds the single 1 to the accumulator and is shut off upon FF3 going low for the first time. Also, the counter is boosted by one at this point and the sum is parallel loaded into the eight-bit register. Notice that the output of the counter is added to the second least significant posi- tion; hence the successive additions of 2, k, 6, 8 ... occur as the counter counts up and additions take place. When the counter reaches a count of ABCD =0100 for our example, overflow occurs at Qk of the more significant adder and FFl* is reset to shut off FF3. Readout of the counter indicates the desired square root rounded correctly, i.e., 2. To illustrate the rounding feature inherent in the square rooter, the square root of 21*0 is 15.1*919 and that of 2i*1 is 15*7370. The square rooter, true to right, finds the square root of 2I4.O to be 1 5 uhile that of 2l|1 to be 16. Further experimentation might be directed to the speed up of the square root process and incorporating the implementation in a more general arithmetic unit, e.g. one that can also multiply and divide. 3.5 A Simplified "NIM" Of the many two-person games (machine versus human) that readily lend themselves to hardware implementation, a simplified version of "NIM" is a good exercise at the intermediate level. SPECIFICATIONS : An arbitrary number of objects are placed in a row. The two players take turns in removing at least one, but no more than three objects from the row. The player to take the last object loses. Design a machine to play the game according to a winning strategy. 53 CONSIDERATIONS ; Upon simple analysis a winning strategy is realized if a player leaves I4N + 1 (N = 1, 2, 3...) objects upon completion of his turn. Hence, if there are fifteen objects remaining after his opponent's turn, the winning player will remove two objects leaving thirteen (N = 3) objects remaining. From that point forward, the winning player will simply remove four minus his opponent's play to maintain the pile in the ljN + 1 status. When N becomes zero, the opponent player is left with the losing play. The row of objects can be represented by a number of lamps. Those that are lit indicate the number remaining. Since this number is arbitrary, a counting sequence is to be applied to the lamp register at a speed faster than the player can follow and arbitrarily stopped upon setting a switch. In order to keep the game interesting, the machine should have no control over the initial row. Also, if we allow the row to indicate a maximum of sixteen objects, then an indication may be too small to make the game challenging. Consider, then, a sequence that counts ... 15, 16, 8, 9 ... This will prevent too small an initial row. Inherent in the logic for the machine's play is a removal of objects until the row indicates ljN + 1. If a down counting register is reset to one (ABCD = 1000) and counts down upon each object's removal, then A © B describes the counter condition to stop the machine play. This also means that when the machine is confronted with a J4N + 1 row, it would remove just one object in the hope of prolonging the game until the player fails to play to I4N + 1 . I MPLEMENTATION : Figure 3.5.1 describes a logic design of the game implemented on the EXCEL system. 5U C2 RESET S2 O S2 NORM Gl ~gJ\- G2 PLAYER SI O SI MACHINE **■ T 65 o Z./7 PLAY SO O 3 05 Z./* Y /• ° 74194 s * CK QA-OD reg 4 H Lie o o -o -o ° 74194 si CK OA— QD H -o ■o o -o so 74194s i \—h CK Q A - Q D O O O -o so 74/94s/\ — // 1li ... 9 at the 100 Hz rate. When L9 extinguishes, all sixteen lamps are relit upon the next clock. This avoids starting off with a row less than eight. This same signal used to reload the registers also loads the down counter to ABGD = 1000. When the reset switch is in NORM, the clock cycle depends upon the setting of the MACHINE/PLAYER mode switch. In the PLAYER position, a single lamp is extinguished upon each toggle of the PLAY switch. In the MACHINE position, CI (1 Hz) shifts the lamps down until QA © QB of the counter becomes true, which then terminates the play by means of register S parallel loading a H into QA of register S. Play continues by alternating between MACHINE and PLAYER mode. Winning is noted by a 1 Hz flashing of L17 (MACHINE mode and L2 extinguishes) or L18 (PLAYER mode and L2 extinguishes). A winning strategy is inherent in the logic. The machine will always play to the ijN + 1 state unless initially confronted with I4N + 1 lamps. In the latter case, the machine will optimally extinguish just one lamp in the hope of prolonging the game. Additional features desirable, but not incorporated, could be an automatic mode switch and also methods to ensure that the player ex- tinguishes at least one but not more than three lamps at any one time. 56 3.6 "Memory Module Tester" Considerable design effort has been expended on logic circuit checkout and testing. Logic modules can include many functions in a single package and operational tests are usually performed by specialized small computers. This experiment describes the design of a logic circuit that tests the 7k&9, sixty-four-bit memory module. SPECIFICATIONS ; Devise an automatic tester that accurately indicates the operational performance of the memory module (7ii8°). CONSIDERATIONS : A study of the problem indicates that simply writing into a memory location and then immediately reading from the same place tests that one particular word but not the influence of troublesome neighboring locations. A valid test, therefore, might be implemented by writing a pattern into all locations and then returning to the first location to rewrite a new pattern in each location, after checking for the presence of the old pattern. This new pattern is written sequentially into memory and becomes the old pattern on the next cycle through memory. This process continues until every possible pattern has been tested or an error is detected. Operational performance of the module to be tested can only be measured to the extent of the performance of the tester itself. Hence, provisions might be included to insure that it has not failed to detect an error in its testing routine. IMPLEMENTATION ; Let us at first study the simplified diagram in Figure 3.6.1. The top three boxes serve as a variable incrementer. The register accepts as input the sum of the switches and its own output. Hence, the output of the register increments by the amount indicated by the switches each time the register is clocked. The counter sequences by COUNTER REGISTER A-D QA-QD ADDER B s a-d MEMORY COMPARATOR* CONTROL SI SWITCHES SO-S3 FIGURE 3.6.1 BLOCK DIAGRAM OF MEMORY MODULE TESTER 58 counting up each clock pulse and its output is used to address the memory module in sequence. Obviously, the comparator decides whether the memory module operated correctly by comparing the memory contents with its previously written input. We can best describe the operation of this circuit by a simple computer program illustrated in Figure 3.6.2. If we now recognize that the program can be simplified by a four-step program core, we can then next "hard wire" the program and describe a specialized simple tester. A working logic circuit illustrating the memory module computer is described in Figure 3.6.3. FF1 and FF2 perform as a ring counter. They are at first preset to 3, then count 3, 2, 0, 1, 3 ... By using a decoder, each count sequences a portion of the circuit according to the wired program. FF3 at first reset, allows C2 (100 Hz) to sequence the ring counter. If the memory module fails, sequencing is stopped and a lamp is flashed at the CI (1 Hz) rate. FFI4. initially reset, is wired as a one-shot switch that toggles to H upon the first check for "counter = 15." FF£ sets upon a carry at "counter = 15" and is used to derive the clock signal for the register. Operation proceeds by toggling the reset switch after setting the desired increment at switches SO, S1 , S2 and 53. For example, let us suppose that the switches are set at 1000 (decimal 1). Hence, as the counter sequences from to 15, a 1000 is written into each memory address. Upon the counter reaching 15> for the first time, the register is edge triggered into ABGD = 1000 and hence a 0100 is applied to the memory data inputs from the adder sum. Upon each sequence count of one from then on, the comparator compares the 1000 at the register with the contents at the memory location. If correct, an incremented word is then SET SWITCHES I RESET V WRITE INTO MEMORY NO SCTR\. BOOST COUNT*. -R YES 59 LOA D REGISTER I BOOST COUNTER WRITE INTO MEMORY HALT YES FEGUR , 3.6.2 MEMORY MODULE TESTER FLOW CHART ' I u URR 3 .6.3 M EMORY MODULE TESTER 61 replaced in memory. This process continues until stopped by the operator. The result is that every possible word configuration is tested. Different switch configurations can test all possible bit patterns. In addition, by activating a switch while the computer is testing a module, an error might occur, hence this is an indication that the tester is operationally sound. 62 CHAPTER h THE TERM PROJECT An experiment over an extended period of time and of considerable logic design effort might be the concluding effort for a logic course. Experiments beyond the intermediate type are necessary for an experience in fusing interrelated sections into a functioning machine. This chapter serves to provide a workable example of a terra project. Steps in a terra project are marked by distinct developments. At first an idea is proposed for consideration and a significant amount of thought goes into its interpretation and a suitable approach. Parts are identified and separated into sub-project levels. Standards are agreed upon such that the sub-projects will properly mate upon completion. Finally, the design is implemented by integrating the sub-projects and adapting further improvements. Final implementation is then presented and defended; also further improvements or alternates are suggested. "Craps Shooter" INTRODUCTION : The game is played by throwing a pair of dice. In each throw only the sura of the two upturned faces is significant. A player wins on the first throw if he scores 7 or 11; he loses if he scores 2, 3 or 12. Any other first throw score, namely h, 5, 6, 8, 9 or 10, is called his "point", and he continues to throw. The player wins on a subsequent throw if he scores his point before scoring a 7; he loses on a 7. 63 OBJECTIVE ; The aim is to build a machine to play the game according to these rules. A single switch controls the rolling and stopping of the dice, which are simulated by a pair of counters. The information displayed on lamps after any throw comprises (a) the upturned faces, (b) the point and (c) flashing win or lose signals when the game is over. At the end of a game further rolling of the dice is to be auto- matically inhibited (to prevent cheating I ) until a "clear" switch is operated, which resets the machine in readiness for a new game. OUTLINE ; A block diagram of the system is shown in Figure U.1. A-DIE and B-DIE are two three-bit counters, each of which is designed to cycle through the six states corresponding to the faces of a die. They are driven by two independently generated clocks of widely differing frequencies, so that their contents are not correlated. The clocks are started and stopped by the ROLL switch connected to the CONTROL logic. Thus, the dice are rolling or stopped according as the clocks are running or not. The contents of A-DIE and B-DIE are fed respectively to DISPLAY A and DISPLAY B via a pair of simple decoders, each of which lights one lamp for a 1, two lamps for a 2, etc., the positions of these lamps corresponding more or less to the positions of the dots on the face of a die. The counters also drive an ADDER whose sura output represents the score of any particular throw. This output is connected to the POINT REGISTER, EQUALITY DETECTOR and some combinational logic in CONTROL. CONTROL loads the POINT REGISTER at the end of the first throw, at which time it also inspects the ADDER output for a winning or losing score. If a game proceeds beyond the first throw, then, following each subsequent throw, CONTROL examines the output of the EQUALITY DETECTOR to see if the 6U A-DIE DECODER O O O O O O DISPLAY A POINT REGISTER O O O O i— » ADDER EQUALITY DETECTOR DISPLAY POINT DISPLAY B CLEAR ROLL Y Y Y Y CONTROL DISPLAY WIN /LOSE FIGURE U.I BLOCK DIAGRAM OF CRAPS SHOOTER 65 player has won, as well as the ADDER output to see if the game is lost. DETAILED LOGIC DESCRIPTION : Figure ii.2 shows the dice counters, decoder and displays. The counters are minimal JK designs with A1 and B1 the least significant bits. For the A-DIE J1 - K1 - 1| J2 = Alj K2 = A3 ; J3 - A2; K3 = AT. Similar equations hold for the B-DIE. Since only six out of the eight possible counter states are needed, it is desirable that the design ensure that the two disallowed states (0 and 7 in this case) lead into the main count cycle. That this is so can be seen from the state transition dia- gram. This scheme not only makes it unnecessary to preset the counters immediately after switching on power but also ensures that, even if a counter is spuriously triggered by noise into a disallowed state, it will return to the correct cycle after the next clock pulse. The clock signals CA and GB are generated by CONTROL and have approximate frequencies of 100 Hz and 1 MHz, respectively. CA- H 6 £ s J Al -qc 3a K Al R 2 5b IT s J A2 c 3d K A2 R I • • 11 14 1 s J A3 8 qc 3e_ A3 r 12 13 " H5f 5g CARD 6*J« - 8 4/ I^J 4-aO Q ""■ v — ' CARD 7 ->A1 ->A2 ->A3 66 CB 19 S7 s J Bl 16 ac 3c ^K Bl R ~Y& 20 21 11 2 s J B2 c 3b K B2 R 12 * — * 13 "OlO CARD j^)^^ Q- 14| N 12 o 15 'CW 1« 22 ii S J B3 C 3f K B3 R 3 20 21 18 6 A^4rdiS- CARD 7 ->B1 ^►B2 ->B3 FIGURE h* 2 DICE COUNTERS, DECODERS AND DISPLAYS 67 Each decoder requires four gates. The center lamp should light on 1, 3, 5 or 6, i.e. for A1 v A2 A3. One diagonally opposed pair should light on 2, 3, k, 5 or 6, i.e. for A2 v A3. The other pair should light on li, 5 or 6, i.e. for A3. The remaining lamp should come on for 6 only, i.e. for A2 A3. It will be seen that states and 7 are treated as don't cares. Figure U.3 shows the adder, point register, point display and equality detector. Only the three low order inputs to the adder are needed, the other inputs AU, Bit and GO being tied to L (logic 0). The adder outputs 51 - Sli are connected to the parallel -load inputs of the four-bit point register on the same card. This register is loaded when the signal G from CONTROL goes to 1 at the end of the first throw. Its output is connected to the four-lamp point display and is also compared with the adder output by the 1 5 -gate equality detector. The detector output E is 1 only when equality prevails; it is sampled by CONTROL after all throws but the first. CONTROL itself is shown in Figure h»k* The 6-gate NAND network in the upper left corner is used to turn clock signals CA and CB on and off, without slicing clock pulses, and also to generate a control signal R (rolling) which goes to 1 immediately before the first clock pulses of CA and CB and returns to after the last ones. In the quiescent state the switch signal ROLL SW = 0, R = and CA = CB = 1 . When ROLL SW goes to 1 the output of NAND £j cannot go to until both C2 and C3 are 0. When this happens, R goes to 1, but CA cannot go to until C2 returns to 1. The action of CB is similar. CA and CB then produce clock pulses as long as ROLL SW = 1 . When ROLL SW goes to the output of NAND $ j goes to 1 , but R cannot go to until both CA and CB have returned to 1 . Since the time at which this occurs is at least half a clock period (about 68 •-* cm ro sf co en co en /N * A A to OOOO § Z Z CO OT (0 o 5 m ^ ^i cj . Figures U.2 through h»h also show pin connections and element placement. For NAND and NAND-NOR cards the gates are designated a through e in the top row and f through j in the bottom. JK flip-flops are similarly designated a through f . The elements on the ADDER car* are a, b and c from left to right. A photograph of the craps shooter is presented in Figure U.6. PLAYING THE GAME : Play is initiated by setting CLEAR to L and back to H. This action clears the sequencer such that QA and QB become L. Also ENABLE consequently goes to H and the oscillator gates can now gate the clocks to the die registers upon ROLL becoming H. When rolling, the lamps flash at a speed higher than a human can follow such that when ROLL goes to L the contents of the die registers is purely arbitrary. On this first roll QA has now become H and the game decoder in the CONTROL decides if a WIN or a LOSE has occured by looking at the sum of the ADDER. A WIN or LOSE would flash an indicating lamp and ENABLE would become L preventing further play. Else a subsequent roll would have to follow and a WIN would result if E became H (match "point") before a 7 is rolled. ALTERNATE SOLUTIONS AND EXTENSIONS : Since two high speed clocks were available, this design availed itself of this convenience. Two independent clock sources might be an unnecessary expense if one would suffice. Hence 72 i £_ SWITCH 3 J-K 11 NAM) k ADDER 12 NAND -NOR : 5 NAND 13 NAND 6 LAMP Ik NAND-NOR 7 LAMP 15 CONTROL FIGURE U.5 CARD LAYOUT 73 FIGURE U.6 CRAPS SHOOTER 7k an alternate solution might use a single dock. However, it is very important that the proportional chance of a dice sum occurring remain the same as in the original game. In the actual play of the craps game, the player rolls the dice and they simply stop rolling after a short period. In this machine version the player not only initiates the rolling process but also stops it. Hence, realism might be added by having the player simply throw a switch for the rolling process which after an unpredictable, variable period slows to a final stop. 75 CHAPTER $ CONCLUSION A theoretical knowledge of logic design is only a part of the total since many system concepts are a direct result of experimentation. The main objective to provide a basic background in design becomes complete when a logic laboratory companions the classroom course. The joint effect results in the student acquiring added confidence in his own abilities and a desire to continue at an advanced level. This study detailed a three phase laboratory course. With the instructor providing detailed supervision during the first phase, the student is guided through the basic techniques. The second phase relaxes strict supervision; the instructor becomes merely an advisor. In the final phase, the student works almost entirely as an individual experimentalist. The total effect is an exceptionally motivated student who achieves an intense feeling of pride in accomplishment. When introduced to a relevant and new technology involving sophisti- cated devices and techniques, the student responds as a professional. He is enthusiastic about the break from the traditional approach, and a "hands on" experience imparts an additional dimension to his understanding. Engineers are traditionally excited about a working design implementation; this can now be extended to the non-engineer in logic design. Funds available for logic laboratory equipment are limited at most colleges and universities and, therefore, educators strive to find efficient and simple laboratory apparatus. Logic design is one of the few technological fields that uses state of the art equipment at a 76 reasonable cost. The present price of a logic chip that provides four two-input NAND's is less than 2$ cents. Comparing this cost with, say, equipment to outfit a modern microwave engineering laboratory, one readily sees the educational bargain. The EXCEL logic laboratory cost less than a few hundred dollars per copy and it was locally con- structed using new parts. It has proved exceptionally rugged and has now survived two semesters with all of its modules intact. It seems likely that a single unit will remain a useful package beyond five years. The per-student experience is surprisingly inexpensive. 77 LIST OF REFERENCES 1. Booth, T. L., "Undergraduate Digital Laboratories," Proceedings. of the IEEE , June 1971, Vol. 56, No. 6, pp. 908-915. 2. Digital Computer Principles , Burroughs Corporation, McGraw-tfill Book Co., Inc., New York, 1962. 3. "Digital Systems Laboratory Courses and Laboratory Development by Task Force VI on Digital Systems Laboratories," Cosine Committee, Comm. Eng. Educ. Nat. Acad. Eng., Washington, D.C., 1971. k» Dietmeyer, Donald L., Logic Design of Digital Systems , Allyn and Bacon, Inc., Boston, Massachusetts, 1971. 5. Eadie, Donald, Introduction to the Basic Computer , Prentice-Hall, Inc., Englewood Cliffs, New Jersey, i960. 6. Faiman, Michael, EXCEL-Experiments in Computer Electronics and Logic , Internal Publication of the Department of Computer Science, University of Illinois, Urbana, Illinois, Sept. 1971. 7. Hill, F. J., and Peterson, G. R., Introduction to Switching Theory and Logical Design , John Wiley and Sons, Inc., New York, 1968. 8. Hughes, John L., Computer Lab Workbook , Digital Equipment Corporation, Maynard, Massachusetts, 1969. 9. Khambata, Adi J., Introduction to Integrated Semi-Co nductor Circuits , John Wiley and Sons, New York, 1963. 10. Logic Handbook , Digital Equipment Corporation, Maynard, Massachusetts, 1969. 11. Maley, Gerald A., Manual of Logic Circuits , Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1970. 12. Marcus, Mitchell P., Switching Circuits for Engineers , Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1967. 13. Mowle, Frederic J., "The Evolution of a Digital Subsystem Laboratory," IEEE Transactions on Education , Vol. E-1U, No. 3, August, 1971, pp. 1 3U-1 38 . 1li. Richards, R. K., Digital Design , John Wiley and Sons, Inc., New York, 1971. 78 1£. Troxel, Donald E. , "A Digital Systems Project Laboratory," IEEE Transactions on Education, Vol. E-11, No. 1, March, 1968, pp. 2i1-B. 16. Uhger, Stephen H., Asynchronous Sequential Switching Circuits , John Wiley and Sons, Inc., New York, 1969. 17. Warfield, John N., Principles of Logic Design , Ginn Co., Boston, Massachusetts, 1963. 19 APPENDIX THE EXCEL SYSTEM This section is a brief exposure of the hardware available on the EXCEL logic laboratory. A description of the unique features of this logic laboratory are presented such that reference can be made from the experiments in this study. Detailed information concerning the inner structure of the integrated circuits, however, is not provided. The interested reader is referred to the IC manufacturer's catalog. All the IC's used in the EXCEL laboratory were manufactured by Texas Instruments, Inc. EXCEL is a modular system for performing experiments in computer electronics and logic. It is housed in an open-topped case which has a built in, regulated and protected power supply, with an on-off switch and indicator lamp, and two ranks of connectors and guides into which up to sixteen printed circuit cards may be inserted. The bottom connector serves to connect power to the card when it is plugged in and is offset from center, so that it is impossible to insert the card in the wrong way round. Each EXCEL card has a top plate through which all logic signal connections are made. The top plate has identifiable pin sockets, into any of which the bared end of a length of 22 gauge insulated wire may be inserted. The EXCEL digital package at present contains eleven types of cards. Usually, more than one of each type is available to the student. The eleven cards are: LAMP, SWITCH, NAND, NAND-NOR, JK, CONTROL, REGISTER, ADDER, MEMORY, SELECTOR and KLUGE. 80 All plug-in cards have a number of features in common. Each card is identified by its color coded plastic label, its title appearing on the left end of the label, and finally by the shapes and disposition of the symbols appearing on the label. There are a maximum of four rows of pin sockets each position numbered in the left-to-right direction from to 22, with the numbers of missing pins omitted. Pins associated with a particular circuit on the card are grouped together and surrounded by a symbol characteristic of the circuit. An output from a circuit is always a single pin, while the inputs to a circuit are each a pair of pins, one above the other. Some cards have additional outputs labeled H and L. These outputs are sometimes needed for connecting to unused inputs of other circuits. Figure A.1 and A. 2 are photographs of the nine cards produced at first for the laboratory. In addition, Figures A. 3 and A*k are photo- graphs of the SELECTOR and KLUGE cards respectively; these cards were developed later as additional funds became available. 1. LAMP Card The lamp card contains nine lamp circuits and two each of H and L output sources. The even numbered pin positions from 2 through 18 are inputs to lamp drivers which in turn light the corresponding lamps. A lamp will light only if a high logic signal is connected to its input. The fanout of a logic signal is negligibly affected by connecting it to a lamp circuit. Because each lamp is a tungsten filament bulb, which takes a relatively long time to heat up or cool down; its use is mainly in ob- serving and checking static or slowly varying conditions. 81 S R JQQK MB*]E>9flHBp<»] 2 3 4 5 6 Ml WKM C S R J Q Q K O O 8 9 1 It 12 13 14 ") o o o Q Q K S R J Q Q K 16 17 18 19 20 21 22 Q K JQQK j O 12 13 16 ; 7 18 20 21 22 4 8 Kj II \2 14 15 18 19 20 21 22 np° w IIP fflP° ml ■» ^ n §3 , L CVE W POI NTS. ^ TOWA RD MICH QUTI F€D EI^E EJB S3 PIN S4 S5 S5 S€ S6 S7 S7 #i rr#i mn itwi rr@ 4 6 8 10 12 14 16 18 22 •i i:»ii:* FIGURE A.1 EXCEL CARDS 82 2. SWITCH Card This card contains eight SPOT switches. Each lever is color coded and each switch numbered from to 7. Each switch has two outputs: SO and SO for switch No. 0; Si" and S1 for switch No. 1, etc. When its lever points toward the SO pin, that output is high and SO's output is low. The reverse is true whan the lever is in its other position. To prevent contact flutter when the contacts of the switches make or break, a bounce eliminator circuit is permanently connected to each switch. On switching, the output changing from high to low does so about one logic circuit delay time ahead of the other output, which changes from low to high. 3. NAND Card The NAND card contains ten gates and a high and low output. The gates are contained in three integrated circuits: two 7I4.OOS each hold four two-input NAND' s, and the two four-input NAND's are contained in a single 7U20. Eight two -input NAND's terminals are in pin position 2 through 16 and the two four-input NAND's in position 18 through 20. U. NAND-NOR Card The NAND-NOR card contains ten gates: six three-input NAND 1 s are contained in two 71*10 circuits and four two-input NCR's are contained in a 7ii02. On the card label the NAND terminals are in pin position through 13 and those of the NOR gates at position 16 through 22. 83 Cl C2 C3 A B C D A B C D G2 8 9 10 11 12 13 14 15 FIGURE A. 2 EXCEL CARDS 81* 5. JK Card The JK card provides six JK, master-slave, flip-flops which originate from three 7k76 packages. For each flip-flop the pin labelling from left to right is as follows: C clock input S overriding jet input R overriding reset (clear) input J JK set input Q true (set) output Q false (reset) output K JK reset input This type of JK flip-flop has an overriding set (S) and reset (R) inputs which are normally tied to H and are active when L. 6. CONTROL Card The CONTROL card contains a H and L source, a binary counter, a four-bit decoder and three clock sources, C1 , C2 and C3. Above pin positions 3-12 and below k - 7 are the terminals of a four-bit, binary, programmable, synchronous, up, down counter, which is contained in a 7U193 IC. The large element to the right is a four-bit decoder and its terminals are derived from a 7k*\5k IC. Below pin positions 0, 1 and 2 are three clock sources, labeled C1 , C2 and C3. The approximate frequencies of the clocks are respectively 1 Hz, 100 Hz and 1 MHz. These clocks are derived from 7k0$ inverters and associated timing capacitors and resistors. 8* 7. REGISTER Card The REGISTER card contains three identical elements; each is a universal four-bit shift register type 7I4.1 9h» The flip-flops composing this register are "edge-triggered" devices; that is, the input informa- tion is sampled on the leading edge of a positive going transition of the clock (CK) input and is then locked out. Thus, the outputs may be connected directly, or via combinatorial logic, to the inputs without the need of an intermediate register. The clear (GL) input is over- riding and is active when low. SO and S1 are the mode control inputs and define the four modes of operation as follows: SO SI OPERATION INHIBIT CLOCK 1 SHIFT LEFT 1 SHIFT RIGHT 1 1 PARALLEL LOAD 8. ADDER Card The ADDER card contains three modules. The left and right hand elements are four-bit registers, exactly as on the REGISTER card. Pin positions 8 - 1J4. are the terminals of a four-bit parallel adder, arranged to arithmetically add two four-bit binary numbers, as follows: Ah A3 A2 A1 Bk B3 B2 B1 CO-* (CARRY IN) (CARRY OUT) Cl;-* Sli S3 S2 S1 This module is contained in 7U83 IC module. 9. MEMORY Card Pin position and 22 contain H and L outputs; positions 15 - 21 are for a four-bit register, as previously described. The other two 86 elements are a four-bit, synchronous, programmable, up-counter with clear (7U163) on the left, and a sixteen-word-by-four-bit random access memory (71*89). The counter counts up upon each clock pulse appearing at CK as long as the P and T inputs are tied to a H source and the clear (GL) is inactive (activates on L, synchronous with clock pulse). The count outputs are available at QA, QB, QC, QD and CY (carry). Presetting the counter is accomplished by applying logic levels to the data inputs A, B, C, D and pulsing the LD (load) input. LD is normally H and is active upon a L pulse. The data input A corresponds to the QA flip-flop output and is the low order counting digit. The memory element is a random access, non-destructive read-out memory, organized as sixteen words each four-bits long, with complete address decoding. A four-bit address applied to inputs A, B, C and D is internally decoded to access one of the sixteen memory locations. ME and WE stand respectively for "memory enable" and "write enable" and are inactive when H. D1 through Dk are the data inputs and Si" through SIT are the sense outputs which, when active, are complemented. 10. SELECTOR Card On the left of the card label in pin positions 0-6 are four EXGLUSIVE-OR gates. The remainder of the card contains terminals for four AND-OR gates, each of which is three two-input AND's feeding an OR, or a so-called "3-wide-by-2-input AND-OR." The EXCUEIVE-OR' s are those available in a 71*86 package and the AND-OR 1 s are made from NAND's: 7li00s driving 7li10s. 87 FIGURE A. 3 SELECTOR CARD 88 FIGURE A.k KLUGE CARD 89 1 1 . KLUGE The KLUGE card may contain any IC or discrete electronic component as the designer sees fit. Components are simply mounted on the printed circuit and hard wired to printed rails which connect to the terminal pins along the top. The pins along the top consist of three rows of twenty-three pins of which the top two rows are designed as inputs and the bottom row as output. LIOCRAPHIC DATA ET 1. Report No. UIUCDCS-R-72-535 3. Recipient's Accession No. itle and Subtitle Educational Projects for a Digital Logic Laboratory 5. Report Date July, 1972 uthor(s) Thomas A. Estelita 8- Performing Organization Rept. No. srforming Organization Name and Address liversity of Illinois at Urbana-Champaign ipartment of Computer Science bana, Illinois 618OI 10. Project/Task/Work Unit No. US AEC AT(ll-l)l^69 11. Contract/Grant No. US AEC AT (11-1)1^6 9 Sponsoring Organization Name and Address S. AEC Chicago Operations Office 300 South Cass Avenue rgonne, Illinois 6 0^3 9 13. Type of Report & Period Covered M.S. Thesis 14. Supplementary Notes Abstracts ds study presents a number of laboratory projects typical of those found in a >urse on digital logic design. In addition, an attempt is made to fuse together le theoretical and practical aspects of logic design. It is the purpose of this ,udy to present an experience in the requirements of a logic design laboratory to ie interested educator. The projects were developed on the EXCEL laboratory. ey Words and Document Analysis. 17a. Descriptors ECTRICAL ENGINEERING EDUCATION, DIGITAL LABORATORY, LOGIC DESIGN LABORATORY, GITAL SYSTEMS LABORATORY, COMPUTER DESIGN LABORATORY, DIGITAL DESIGN LABORATORY. '•jdeniif icrs/Open-Ended Terms I13EL - Experiments in Computer Electronics and Logic. :OSATI Field/Group 'ailability Statement lilimited Release "•JTIS-38 ( 10-70) 19. Security Class (This Report) 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages .21 22. Price None USCOMM-DC 40329-P71 •to '9?l .